Hi Friends,I am interested in one of your high-speed dual-channel comparator AD96687 and I would like to use it in one of our projects.We are not using the Latching function. so as per the datasheet, the Latch Enable pin should be Grounded Right?.Even after completing the datasheet, I don't have a clear idea of the latching operation of the chip.Can someone help me in solving this?
This comparator has differential latch mode input. These inputs must have different logical levels.
About disabling the latch function directly said:
Will this help you?
Thank you for your reply.
In the above circuit, if the transistor Q4 is on, my output will be about 4.4V and if it is off my output will be 5V.So my ECL logic high means 5V (I am not sure) and my swing will be about 0.7V.
If I understand you correctly, this is converter from non-ECL to ECL logic and you want use it for latch inputs driving?
Yah, you got me. Now my doubt is should I keep the Latch Enable pin at 5V because 5V is my ECL logic high state in order to disable the latching capability. But as per the datasheet, the maximum voltage at Latch Enable is -Vs to 0V.
Classic ECL logic has a negative power supply of -5.2 volts. The logical element here is, in fact, a differential pair, one of the inputs of which is supplied with a reference voltage. This pair compares the input voltage with the reference voltage. The reference voltage here is minus 1.3 volts.
Once again pay attention to the logical levels
An input voltage higher than -1.3 volts is interpreted as logic 1. Ground voltage also is logic 1
Therefore, your converter must translate the input logic level below ground potential. Can you do that?