AD8488 Reference Schematic

Hi Bivin,

We currently don't have an evaluation board or application schematics for AD8488. Though the datasheet contains the timing diagrams, register maps and the device specification that'll help build your system.

Best Regards,
Dann

Dear DBautista

What are the regulator (bias supply) requirements for AD8488 ? Do i need to consider any radiation protection for AD8488 ?

Hi DBautista

For Gated Clock A and Gated Clock B, it is shown 67 clocks. At which clock the data capture starts ? Will the data appear at output pin at rising edge of next clock. Please clarify what MUXCH001 signal is?

Hi Bivin,

The AD8488 datasheet is the only document we have for the timing diagram.
As for the Gated Clock A, Gated Clock B and MUX-CH00X, these are the timing signals generated internally when the mux channels are enabled.
It is shown in figure 19 that the output appears at the rising edge of clock but settles at a total of 1 clock cycle that's why the ADC is sampled at the rising edge of the next clock.
Also take note that unless you're in TST_MODE, those 128 channels are muxed and sampled sequentially.
Apologies for the delayed response Bivin.

Thanks.

Best Regards,
Dann

Hi Dann

I'm currently doing PCB fabrication for the same, will come back if any issue occur. Thanks for the support.

Regards

Bivin

Hi DBautista

I'm currently testing the IC using the waveform details provided in datasheet. But i'm not getting any output. Please refer images below. Timing details are also added. Kindly suggest steps to debug the same. I have observed voltage variation at input of the IC.

Please reply.

Hi Bivin,

May I know what's your input signal and how is it connected to the Analog inputs of AD8488?
What's the logic level on your TST_MODE pin?
We want to make sure you're not in TST_MODE where you have to select the specific channel you want to see referring on table 8 of the datasheet.

Best Regards,
Dann

TST_mode logic level is '0'. What are the conditions to make sure IC is not entering test mode ?

Currently i have added wait state of few milliseconds for power to stabilize before control signals are started. There could be a rise and fall in TST_mode signal initally but after program gets loaded , TST_mode is driven '0'. Will there be any effect due to initial rise and fall of tst_mode signal.

what should be the state of cs_a ,cs_b, wr signals to prevent  entering tst_mode.

Hi DBautista

Please reply.

Hi Bivin,

Apologies for the delayed response.

As long as the TST_Mode pin level is 0, you're not entering the test mode (I just want to make sure that it is set to 0 during the gate line cycle).
I've checked your timing signals and as of now I haven't seen any issues with it.

May I know what's your input signal  and how is it connected to the Analog inputs of AD8488?
Also, One thing I may have missed on your timing diagram is the RST'(the active low pin), what's the behavior of the RST pin on this 1 gate line cycle?

Best Regards,
Dann

Hi DBautista

I need following clarification regarding RST signal. Refer image below (from datasheet)

1) As per figure, RST is only low for a time period of clk/2, ie 33.5ns only. Will this affect output. Please confirm the same.

2) Also hold is shown as 67ns low during which rst jumps to high state, what should be minimum time period between reset high and hold high ?

Hi DBautista

Please reply

Hi DBautista

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