ADL5206 SPI 3-wire access

HI Eyal,

You are right the waveform on Figure 61 is showing 0x80.. It should be 0x10.

The intention in the figure 61 is to set R/W bit to '1', as ADL5206 can be read back only in SPI mode during a cycle (from CS bar low to CS bar high) after the R/W bit is set high in the previous cycle. There is no continuous read operation. A logic high (1) must be written into the R/W bit to enable the subsequent read cycle and once the R/W bit is set, the rest of the bits are ignored in that write cycle.

Can you please explain where in the DS you see that in the Data Read transaction, the Bit 7 is not read back?

Warm Regards,

Rachana

Hi Rachana,

Figure 58 contradicts what you said about Figure 61 should be 0x10.. As I understand, the first bit in the transaction IS the R/W bit, and is also bit 7. In that case I should be writing 0x80 (10000000) to set up read.

You can see in figure 62 (reading 0x54) - I'm assuming 0x54 refers to bits[6:0], as described in table 8. So this means that bit 7 is not read. Is this a mistake too?

I'll sum up what I think it should be (please correct me if I'm wrong):

I'm assuming bit 7 is the R/W bit, although it is referred to as 'RESERVED' in tables 7 & 8.

Read set up should be written as 0x80. Then user can just perform a read operation, in which case I'm not sure if the first bit read is bit 6 or 7.

Regards,

Eyal.

Hi Eyal,

Yes, the R/W bit is also streamed out during a read back.

Warm Regards,

Rachana

Rachana,

Please confirm:

- bit 7 is the R/W bit.

- Read setup is 0x80.

Eyal.

HI Eyal,

Yes, that is correct for both points.

Warm Regards,

Rachana