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AD8339 evalz board help

Category: Hardware
Product Number: AD8339 evalz

Hi All,

Hopefully someone has experience with this or an equivalent. I am attempting to get a simple example working for the AD8339 evalz board, which does frequency demodulation at low (0--50 MHz) frequencies meant for ultrasonic processing. Here's the attached the data sheet for reference, as well as multiple pictures and some code.

Ref sheet:

AD8339 (Rev. B) (

For reference, I am approximately using Figure 62 of the data sheet as a setup, except that I am trying to use SPI and a raspberry pi. The board itself is older, and the cd that comes with it (yes, cd...) has software that only works on windows XP.
I am only using the first channel as input, my signa gen is a dual channel, so they're inherently synchronized.
The SPI has a 20 bit shift register that allows for enabling of channels 1-4, and for setting phases for the demodulation step (that part is not important for now, since I'm trying to run test where all phases are 0.
Since the bits are fed in reverse, a basic 20 bit word enabling only channel 1 is: 0000 0000 0000 0000 0001
The shift register timing reference is on Figures 56-57. The local oscillator needs to be 4 times the input frequency (4Lo), so I'm running tests with a 50 kHz wave (channel 1) and a 210 kHz 4Lo. The result on the sampled outputs SHOULD be a 10 kHz wave on one of the two channels, and nothing on the other (since the demodulator create IQ data).

Currently, I am unable to get any notable output on the IQ pins. Here is my setup, including pictures. I am trying to use SPI to connect to the board via a Raspberry Pi and a simple python script. Perhaps someone can see something glaringly wrong. Particularly, I'd like to know if anyone has experience with shift registers through SPI with a RPi, and whether or not my simple script is the wrong approach.
Five cables are connected from 20 pin SPI port to the RPI (SCLK, SDI, CSB, SDO, GND). I have labeled them SCLK, SDI, SDO, /CS (CSB), along with a ground (black unlabeled wire).
Here are some pictures for reference. Allow me to explain.
1. "SPI_cables.jpg" shows the color convention used here for SPI, with the black/gray cable labeled as the ground.
2. "pinout_cables.jpg" shows those cables connected to the 20 pin connector. I wasn't sure whether the bottom or the top row was odd or even, so in that picture I assumed the top row was even. I think that's wrong, and currently have it reversed, where the bottom row is even and the top row is ground. Neither version gave me an output, but when configuration is flipped vertically from that picture, setting the CSB pin to high results in a ~0.01 Amp increase in drawn current, so I assume it's correct that way.
3. "CSB_low.jpg" shows the power consumption with CSB set to low. Do you know what the expected value should be? I have twinned two power supplies in the usual fashion to create +- 5V.
4. "signal_gen.jpg" and "gen_osc.jpg" show the generator and o-scope setup. The generator is a 2-channel Rigol, so the input and 4Lo shown in figure 61 of the data sheet are channels 1 and 2 of the generator. Channels 1 and 2 of the o-scope are connected as in Figure 61.
5. "board_setup.jpg" shows the connections to the board.
6. From my understanding of Figure 57 and previous things I've done with shift registers, I put together a very simple python script attached ("py_script.jpg") to set shift register states. As such, if I feed in a 50 kHz wave with a 4Lo of 210 kHz with a common phase of 0, I would expect the result to be a 10 kHz wave showing only on one of the two output channels, but I get nothing.
-In that 10 liner python script, do you see anything glaringly wrong in terms of how I am interacting with the shift register? This approach has worked for various other registers, but maybe there's something here I'm missing.
-I am NOT using the SDO pin despite it being connected, since I THINK it is only used to link multiple chips together. Is this correct?
Thanks for the help,