I'm currently using the LT6600-5 for a current sense resistor application, however and having some trouble with the design producing a wildly different gain than expected. The intended operation is for the LT6600 to amplify the measurements from a sense resistor with a gain of 18dB and measurement bandwidth of 5MHz.
The following is the schematic I've designed for this application. Gain resistors of 100R are used, along with 82pF parallel capacitors for compensation (I've tested with and without these populated). In addition a high frequency ferrite bead (Murata BLM15BD121SN1) is added to reduce HF noise pickup, this should have little impact on the gain, if anything causing some attenuation above 4MHz. The Vocm voltage is driven from a stiff 1.024V supply to match the requirements for an ADC which follows. The Vmid input is simply using the internal divider with a bypass capacitor.
When simulating this design in LTSpice, the results are quite acceptable, not quite flat due to the compensation, but good enough for our application:
However measurements of the actual circuit are showing a widely different gain response, whereby the gain starts around the intended 18dB gain, but then rises rapidly to 25dB by 5MHz, which seems very strange.
I'm trying to work out the possible causes of this gain response. In the simulation I'm able to force similar results by increasing the compensation capacitors to around 600pF which is far higher than in the actual circuit. In fact I've tried removing the compensation capacitors entirely but get the same results.
Is there anything that I may have missed in the circuit? Am I operating the LT6600 outside its specification?