differential amplifier common mode output

Hi Gustavo,

Thank you very much for your reply

We are currently in the designing phase of the circuit, so schematic is not yet ready but let me explain you how it is.

We are required to feed output of Analog Devices demodulator ADL5387 to ADC. We are feeding this outpout from ADL5387 to ADC through bufered differential amplifier ADA4927. Now demodulator (ADL5387) has got default DC offset of 5mV. As per our input, output of the device would vary from 3mV DC to 0.8V DC or 10mVp-p ac to 1.8Vp-p ac and 5mV DC would be added aditionally to these values. When AC is comming at output we can filter out DC offset through DSP filtering after digital conversion. Our problem is when output from device is DC i.e 3mV+5mV(DC offset). This would be difficult to detect as device already have 5mV DC offset. So our aim is to reduce this 5mV DC offset

Now as AC at the output of the demodulator goes upto 1.8Vp-p. So we can not provide any gain in differential amplifier cause it would bring input to the ADC out of its range 2v p-p. Differential amplifier would be unity gain and would only act as buffer in driving ADC. ADC part number is ADS62P42. Datasheet of ADC and demodulator is attached for your referrence.

I hope this explanation will make design line up and constraints more clear.

Note: ADC is present in client system and we can not replace it 

Thanks and Regards,

Dwijen

RF Design Engineer,

HCL Technologies

Hi Gustavo,

Thank you very much for your reply

We are currently in the designing phase of the circuit, so schematic is not yet ready but let me explain you how it is.

We are required to feed output of Analog Devices demodulator ADL5387 to ADC. We are feeding this outpout from ADL5387 to ADC through bufered differential amplifier ADA4927. Now demodulator (ADL5387) has got default DC offset of 5mV. As per our input, output of the device would vary from 3mV DC to 0.8V DC or 10mVp-p ac to 1.8Vp-p ac and 5mV DC would be added aditionally to these values. When AC is comming at output we can filter out DC offset through DSP filtering after digital conversion. Our problem is when output from device is DC i.e 3mV+5mV(DC offset). This would be difficult to detect as device already have 5mV DC offset. So our aim is to reduce this 5mV DC offset

Now as AC at the output of the demodulator goes upto 1.8Vp-p. So we can not provide any gain in differential amplifier cause it would bring input to the ADC out of its range 2v p-p. Differential amplifier would be unity gain and would only act as buffer in driving ADC. ADC part number is ADS62P42. Datasheet of ADC and demodulator is attached for your referrence.

I hope this explanation will make design line up and constraints more clear.

Note: ADC is present in client system and we can not replace it 

Thanks and Regards,

Dwijen

RF Design Engineer,

HCL Technologies