I've been fighting an AD8131 based design for a few days now. I've been trying to find an 8% loss in DC gain.

I posted yesterday that I thought I'd solved this, but now I'm not so sure.

I'd like confirmation that I've analysed the chip correctly, or to be shot down in flames if I haven't.

The Data Sheet gives the internal Rg and Rf values as 750 and 1500 ohms, and says these are "nominal" - I assumed that meant production variation.

The Spice Model has the inverting side Rg2 and Rf2 values as 750 and 1500, but on the non-inverting side they're 742 and 1550. Any idea why?

We are driving the AD8131 from a current-source DAC connected to a 75 ohm resistor. We also have a matching 75 ohm resistor on the inverting input.

Instead of a naively expected gain of 2.00 I am measuring a gain of 1.83.

A simple analysis of the amplifier using the description in the Data Sheet shows it can only give a gain of 2.0 with resistors of 750 and 1500 with **ZERO OHM** sources on the inputs. Not many designs have that.

A more complex (still possibly wrong) analysis gives the following:

D1=Rf1/(Rp+Rg1+Rf1)

D2=Rf2/(Rn+Rg2+Rf2)

Vout = VIn * D1/(2 - D1-D2)

In the above, "Rp" is the positive input source impedance, and "Rn" is the "balance resistor" to ground on the inverting input. "Vin" is the voltage source before the positive input source impedance and "Vout" is the single positive output voltage.

The results of the above calculation are:

**Rg1 = Rg2 = 750, Rf1 = Rf2 = 1500**

**Vp = Vn = 0 Vout/Vin = 1.0000**

**Vp = Vn = 25 Vout/Vin = 0.9677**

**Vp = Vn = 37.5 Vout/Vin = 0.9524**

**Vp = Vn = 50 Vout/Vin = 0.9375**

**Vp = Vn = 75 Vout/Vin = 0.9090**

That explains the losses I'm seeing. What about the model? First using one set on both sides (not matching the model):

**Rg1 = Rg2 = 742, Rf1 = Rf2 = 1550**

**Vp = Vn = 0 Vout/Vin = 1.0444**

**Vp = Vn = 25 Vout/Vin = 1.0104**

**Vp = Vn = 33 Vout/Vin = 1.0000 **

**Vp = Vn = 37.5 Vout/Vin = 0.9942**

**Vp = Vn = 50 Vout/Vin = 0.9785**

**Vp = Vn = 75 Vout/Vin = 0.9486**

That would be a very useful chip design. It has a "sweet spot gain" of 1.00 mid way between the normal 50/2 and 75/2 ohm source impedances. For a while there I thought the chip might be designed this way, but proper measurements showed me it isn't.

Now matching the model:

**Rg1 = 742, Rg2 = 750, Rf1 = 1550, Rf2 = 1500**

**Vp = Vn = 0 Vout/Vin = 1.0292**

**Vp = Vn = 25 Vout/Vin = 0.9959**

**Vp = Vn = 37.5 Vout/Vin = 0.9801**

**Vp = Vn = 50 Vout/Vin = 0.9648**

**Vp = Vn = 75 Vout/Vin = 0.9355**

I'm measuring a Vout/Vin gain of 0.92, which is midway between the Model and the Data Sheet.

The Spice Model is giving gains of +102.8% and -102.5% with zero ohm inputs and +93.5% and -93.3% with 75 ohm inputs for the positive and negative outputs. There's a slight imbalance there, possibly due to the different Rf and Rg resistors. At least it matches my simple model!

The Data Sheet is slightly confusing. After reading it multiple times and looking at Figures 5 and 39, it does look like the gain is specified as the ratio of the voltages on the PINS of the chip, and not the "source voltage", which will be affected by the imput impedance. Also surprising is the attenuation caused by the resistor used to "minimise dc and gain errors" on the other input.

A circuit with 25 ohm imput impedance will lose 3% unless the input resistors are increased to accomodate these affects. 75 ohm imput impedance loses 7 to 9%.

I guess I should ask some sensible questions.

The chip seems to be following the Data Sheet values for Rf and Rg. I assume this is correct, and the gains I am seeing are what is expected?

How come the Spice Model (AD8131_typ.cir) has unbalanced Rf and Rg resistors on its inputs? Is this meant to model something in the chip, as it seems to be associated with a slight common mode error.

A suggestion that it would help if there was a graph of "circuit gain versus input impedance" as it isn't a simple calculation.

Tom

Message was edited by: tom.usenet