ADL5565 gain accuracy, overdrive

Hi

I have inherited a former colleagues design and need to report on it's performance. It uses two ADL5565 amplifiers to provide gain and drive to an ADC. I have read the datasheet and have some concerns.

Gain accuracy

The datasheet states +/-1dB gain accuracy (+/- 12%) which I assume is resistor mismatch. The circuit is designed to have 50R input impedance to match the source, the internal resistors play a significant part of this. The circuit adjusts the input dc level using external 470R resistors and this would also be affected by the values of Rg1, Rg2 etc.

I could assume the values change neatly around the nominal value but actual values would help.

High frequency overdrive

The circuit is designed to amplify signals in the region of 20mVpk but could encounter signals up to 1.5Vpk. The application is for DC to 1GHz signals but users could put faster signals in. Looking at the absolute maximum ratings (page 9) there's a good chance we'll exceed the 2000Vpp MHz limit.

I'll assume this is unacceptable and the input requires clamping?

Will a spice model be available for this device? I'm using a standard part to check that input common mode voltage and output current is within spec but it's unlikely overload behaviour will match.

Regards

Lee

Hudson_gain.pdf
  • Hi Jim, I wouldn't worry too much about common mode range at this point. I'm putting together a spreadsheet to calculate the dc levels and ac gains through the system. This is where the resistor spread would be handy.

    I've put Nicks design values at the end of the document for your information but I would expect to tweak them.

    I'd like to avoid commenting on circuitry beyond the attached schematic if I can. Although we have an NDA with ADI the forum is open to everyone.

    The first stage was designed using formulae from a Michael Steffes (Intersil) app note, gain should be ~4.6V/V with input impedance of 50R. The second stage should have a nominal gain of 5.22 so 24V/V total. This gives a max input of ~80mV@1GHz, I can only think of one way to clamp at this low a level but haven't used it with DC signals.

    Regards

    Lee

    First stage

    Vcc 3.4V

    Vee -1.6V

    Vcom 1V

    Second stage

    Vcc 4.1V

    Vee -0.35V

    Vcom 1.8V

  • Hi Nanoman, I've reviewed your schematic and have some questions. Which ADC are you planning to use in this application? Need to make sure the common mode voltage levels will be compatible.

    What supply voltage is being used? 3.3 V or 5 V?

    The ADL5566 commom mode input level is 1.2 V - 2V and the output leve lis 1.4 V - 1.8 V for a 3 V supply.

    Common mode level  for a 5 V supply is  1.2 - 3.8 V input and 1.4 V - 3 V output.

    Yes, The input will require clamping. Based on the absolute maximum rating table at 1 GHz the maximum output swing is 2 V p-p.

    We do not offer a spice model for the ADL5565. Small signal S-Parameters are available.

    I believe the input stage needs some modification. I am in the process of getting clarification on this.

  • Resistor values are +/- 3% typical and +/- 10% max.

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