HMC760 clock & linearity

So, ADCMP580 with CML output would be best сhoice for 250 MHz.

Thank You

Hi

Clock inputs are 50 ohm terminated per side and should have a common mode level that falls within +-0.5V.  As the data sheet shows, the differential level should be between -2 and 2 V (i.e. each side swings a max of +-1Vop.)  2^nd order linearity might be affected if the input clock slew rate per side falls well below 2V/ns.  If using a very low frequency clock like 250 MHz, then a square wave clock with fast rise/fall times should be used instead of a sinusoidal clock to keep the slew rate up.  At higher frequencies above 500 MHz, sinusoidal clocks are fine as long as they meet the level requirements outlined in the data sheet.

Best Regards

Sinan Alemdar

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