Do i can get best output linearity when i drive HMC760 by CML (GND to -Vee -2.5V) or LVPECL 2.5 (VCC 2V to Vee - 0.5V)? For example ADCMP5820 or ADCMP582.
Clock inputs are 50 ohm terminated per side and should have a common mode level that falls within +-0.5V. As the data sheet shows, the differential level should be between -2 and 2 V (i.e. each side swings a max of +-1Vop.) 2nd order linearity might be affected if the input clock slew rate per side falls well below 2V/ns. If using a very low frequency clock like 250 MHz, then a square wave clock with fast rise/fall times should be used instead of a sinusoidal clock to keep the slew rate up. At higher frequencies above 500 MHz, sinusoidal clocks are fine as long as they meet the level requirements outlined in the data sheet.