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1. The input common-mode voltage range of ADA4930-2 should be 0.3~2.8V. But, i found this parameter has different range in Chinese version datasheet, where is 0.3~1.2V. Also, there is same issue about output voltage range.

2. There are two blocks between ADA4930 and AD9633, which need me to make choices: one is the mach resistor, the DEV kit used 24 ohm, our previous board (between AD8138 and AD9218) used 50 ohm, there is no match resistor in figure 60 of ADA4930 datasheet, however 33ohm in figure 59; aonther is the RLC filter, is this necessary for my application? And  will the inductance destroy the DC coupling fucntion?

3.The DEV kit schamatic of the ADA4930 is same as figure 55 of the datasheet, so the ADA4930 was configured as G=1 and input 2Vpp, output also 2Vpp. My system, the front signal is 1Vpp, so i should refer to figure 60, am i right? Which convert the input 1Vpp to differential 2Vpp.

4, In dev kit, use Rcm(1.82K) pull-up to +3.3V. There also have several pull-down resistors. Can i remove these pull-down resistor in my design?

5. Can you teach me how to calculate each node's voltage based on figure 60 of ADA4930 datasheet? For, datasheet said "For a common-mode voltage of 1 V, each ADA4930-2 output swings between 0.501 V and 1.498 V, providing a 1.994 V p-p differential output. " I can understand how to get 1994 V p-p, but i don't know how to get 0.501 V and 1.498 V.

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• Hi Coyoo,

1. The ICMVR of ADA4930 varies with the supply voltage. I think you just misread the datasheet. To guide you, here is a table for ICMVR at different supply values.

 Supply Voltage 3.3 V 5.0 V Input Common-Mode Voltage 0.3 to 1.2 V 0.3 to 2.8 V

2. If you need to have a post-amp filter prior to the ADC, then use the RLC filter network. This filter if configured for 40 MHz corner frequency, if you ought to have a different cutoff, you can change the values to match the your desired corner frequency. I suggest you use 33 ohms just like in figure 59 for a better filter response. And NO, the inductance doesn't affect the Common signal on the outputs.

3. Yes you can refer to figure 60. Although the best way to do it is by using the DiffAmpCalc tool, the benefit of this tool is that you can see the "real-time" signals and values are customizeable depending on the driver setting you like.

4. If you notice on the dev kit, the 1.8k pull-down resistors are in DNI, this means that upon shipping those resistors are unconnected. It's up to the customer (you) if you like to center your inputs at Vs/2, which is 1.65V at 3.3V, by installing the 1.8k pull-down resistors. However, leaving those pull-down resistors as DNI, the effective DC offset will depend on the voltage divider network of 1.8k pull-up resistors and the Rin_se. On your current design, the DC offset (Vicm) is at 440 mV.

5. Since the Vocm is set at 1V, therefore the outputs will have an DC offset of 1V away from ground. The differential gain is 2V/V (1.994V/V to be exact) but the single-ended gain (that means, each single-ended output, the +OUT and -OUT) is 1V/V. Given that the outputs has Vocm at 1V and the input is 1Vpp, therefore the outputs will be centered at 1V with a pk-pk amplitude of 1V. So effectively, the minimum voltage at each single-ended output is:

Vocm - Vin(1V/V)/2 = 1V - 1V(1V/V)/2 = 1V - 0.5V = 0.5V.

while the maximum voltage at each output is:

Vocm + Vin(1V/V)/2 = 1V + 1V(1V/V)/2 = 1V + 0.5V = 1.5V.

The best explanation for this voltage levels can be found in this application note. High Speed Differential ADC Driver Design Considerations.

For more guidance with designing ADC drivers, I strongly suggest that you use the DiffAmpCalc tool in parallel with the application note for the computations.

Regards,

Jino

• Hi Coyoo,

1. The ICMVR of ADA4930 varies with the supply voltage. I think you just misread the datasheet. To guide you, here is a table for ICMVR at different supply values.

 Supply Voltage 3.3 V 5.0 V Input Common-Mode Voltage 0.3 to 1.2 V 0.3 to 2.8 V

2. If you need to have a post-amp filter prior to the ADC, then use the RLC filter network. This filter if configured for 40 MHz corner frequency, if you ought to have a different cutoff, you can change the values to match the your desired corner frequency. I suggest you use 33 ohms just like in figure 59 for a better filter response. And NO, the inductance doesn't affect the Common signal on the outputs.

3. Yes you can refer to figure 60. Although the best way to do it is by using the DiffAmpCalc tool, the benefit of this tool is that you can see the "real-time" signals and values are customizeable depending on the driver setting you like.

4. If you notice on the dev kit, the 1.8k pull-down resistors are in DNI, this means that upon shipping those resistors are unconnected. It's up to the customer (you) if you like to center your inputs at Vs/2, which is 1.65V at 3.3V, by installing the 1.8k pull-down resistors. However, leaving those pull-down resistors as DNI, the effective DC offset will depend on the voltage divider network of 1.8k pull-up resistors and the Rin_se. On your current design, the DC offset (Vicm) is at 440 mV.

5. Since the Vocm is set at 1V, therefore the outputs will have an DC offset of 1V away from ground. The differential gain is 2V/V (1.994V/V to be exact) but the single-ended gain (that means, each single-ended output, the +OUT and -OUT) is 1V/V. Given that the outputs has Vocm at 1V and the input is 1Vpp, therefore the outputs will be centered at 1V with a pk-pk amplitude of 1V. So effectively, the minimum voltage at each single-ended output is:

Vocm - Vin(1V/V)/2 = 1V - 1V(1V/V)/2 = 1V - 0.5V = 0.5V.

while the maximum voltage at each output is:

Vocm + Vin(1V/V)/2 = 1V + 1V(1V/V)/2 = 1V + 0.5V = 1.5V.

The best explanation for this voltage levels can be found in this application note. High Speed Differential ADC Driver Design Considerations.

For more guidance with designing ADC drivers, I strongly suggest that you use the DiffAmpCalc tool in parallel with the application note for the computations.

Regards,

Jino

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