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ADL5565 IMD3 performance with narrower spacing

Hello

I am looking for some assistance on the ADL5565 ADC driver.

The datasheet specifies the ADL5565 IMD3 performance at 200MHz with Av = 6dB, RL = 200R, Vout = 2 V p-p composite as -96dBc.

What frequency spacing is this tested at? The IMD2 frequency spacing is given as 2MHz - is this the same for the IMD3?

Lastly, are there any documented results for IMD3 testing at 200MHz with a 200kHz spacing?

Thanks

Thread Notes

  • Hi, Gavin,

        IMD3 was tested with the same spacing of 2 MHz, same setting as for IMD2.  We do not have measured results for 200 kHz spacing, but we expect them to be the same as for 2 MHz spacing.

    Benjamin

  • Hello Benjamin

    Thank you for getting back to me so promptly.

    I am using an ADL5565 to drive an AD9467 ADC. My input stage consists of

    WBC4-1LB transformer

    ADL5565

    AD9467

    This is described in a separate thread where I asked a question about double transformer configurations (which you also answered, thank you).

    I took some measurements using this input configuration:

    ADC sample rate: 204.8MHz

    Input power level: -7dBFS

    200kHz spacing: 189.9MHz and 190.1MHz

    And my IMD3 results were:

    Channel 1: 77.5dBc

    Channel 2: 77.4dBc

    Channel 3: 78.3dBc

    I then repeated the test with a 2MHz spacing:

    2MHz spacing: 189MHz and 191MHz

    And my IMD3 results were:

    Channel 1: 83.2dBc

    Channel 2: 83.5dBc

    Channel 3: 83.8dBc

    There is an almost 6dB difference in results simply by increasing the frequency separation to 2MHz.

    Do you have access to an ADL5565 evaluation board to conduct the measurements at a 200kHz spacing?

    Do you have any suggestions as to what I could try to improve the IMD3 performance at 200kHz spacing? Our requirement is 80dBc.

    Thanks again

    Gavin

  • Hello Benjamin

    The engineers here chatted amongst ourselves and we couldn't come up with a definitive reason as to why the IMD3 would get worse as the frequency spacing got smaller.

    We came up with the following ideas although are unsure of whether they are valid or not:

    1) Phase noise from the signal generators mixing

    2) Phase noise on the ADC sample clock source

    Have you had any experience with a similar behaviour? We have seen this before on other designs and so would like to get to the bottom of what is happening.

    Thanks again

    Gavin

  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin