AD8138
Production
The AD8138 is a major advancement over op amps for
differential signal processing. The AD8138 can be used as a
single-ended-to-differential amplifier or...
Datasheet
AD8138 on Analog.com
AD9434
Recommended for New Designs
The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates...
Datasheet
AD9434 on Analog.com
Hi Experts,
I'm using AD8138 to drive the AD9434 differential inputs and met a problem.
I made the schematics exactly the same as the Figure 41 ref design on AD9434 datasheet, and put AD8138 V- to GND and V+ to 3.3V (is it valid?), and connect the AD9434 CML (~1.7V) to AD8138 VOCM as I was told, but after power on, I got 2.3V on the VOCM, and after I cut the connection between CML and VOCM, I supporising discovered that the CML from AD9434 is normal (1.74V), but VOCM is at around abnormal 2.8V level (I read from datasheet then I suppose the VOCM should output 3.3/2 = 1.75V level if I float VOCM pin, is this correct understanding??) and I think if it is because the 1.74V and 2.8V mixed together to create the 2.3V (mid level of 1.74 and 2.8). When the VOCM appears 2.3V, and I feed in the 1.2Vpp sine waveform, the OUT- has the waveform appear but the OUT+ has no waveform.
And then I made my next trial to force the AD8138 VOCM to some levels from 0V to 2.5V by an Agilent power supply, but I could never get an balanced output, and when I tune power supply to drive the VOCM to below 0.8V the OUT- is always 800mVpp sine and OUT+ is always around 480mVpp sine, but when I raise the VOCM level to over 0.8V, the OUT- is getting lower, if contine raise VOCM, the OUT+ sine waveform will disappear.
Even more surprised to me, after the whole bunch of operation, I connect CML and VOCM back again, the power level at the VOCM point is always 1.64V.
Could you please guide me to use the AD8138, I have read through the datasheet AD8138 and check the reference design schematic, and checked my application by the tool Diff-Amp Calculator, but I dont think I made any obvious mistake here. could you please help me?
PS: The input signal is 2.4Vpp and become 1.2Vpp at R214, and I expect the 1.7V common mode and Vpp = 0.6V on both VIN+ and VIN- on AD9434. What should I change to adjust my current design?
mason100 - Moved from ADC Drivers to Differential Amplifiers and ADC Drivers. Post date updated from Thursday, July 6, 2017 8:09 PM UTC to Thursday, July 25, 2024 8:39 PM UTC to reflect the move.
mason100 - Moved from ADC Drivers to Differential Amplifiers and ADC Drivers. Post date updated from Thursday, July 25, 2024 8:39 PM UTC to Thursday, July 25, 2024 8:39 PM UTC to reflect the move.
Hi,
The CML voltage of the AD9434 should be the same as the internal ~1.75V. Since you are provising the common mode bias, you should disable the internal bias by writing 0X04 to register address 0x2C. This will open the switch (which is closed by default for ac coupled signals) in figure 34. The clock must be active for the internal bias voltage to be generated.
Regards,
David
Hi Khai,
I don't seem to find any violation on your application. What are you using to implement the circuit? Is it a PCB? could you attach that as well? WIth the current configuration, the AD8138 would work just perfectly fine.
Regards.
Hi Khai,
If you would check the specifications table, you will see that the 0.1 dB flatness is stated to be 30 MHz typical without any compensation capacitor on the feedback. Also, figures 5, 6, 8 and 9 would clearly show you the AC response of AD8138. These figures tell us that at frequencies above 30 MHz, the signal will peak up to approximately 1.5 dB at ~150 MHz.
As shown above, at 85 MHz, the amplifier peaks and the gain is not effectively 1 that's why you are getting a higher output than expected. What you can do is add a compensation capacitor on the feedback to remove the peaking. However, the bandwidth would dramatically decrease. See Figures 6 and 9. Or, pick another differential amplifier, perhaps a faster one to achieve a maximally flat response on your target bandwidth.
Regards.
Hi Khai,
1. Yes, it's true but note that board capacitance could introduce instability as well, hence some peaking.
2. 0.5 pF will reduce the peaking, somewhere in between 0 pF and 1 pF but we are not certain about the exact value of the peaking since it wasn't tested at that CF.
3. There are other FDA in our portfolio that you might consider. Please see ADA4932 and ADA4937.
Regards,
jino
Hi,
Thank you JinoL for the reply and finally I found this is due to the wrong chipset from our suppliers, it suppose to be AD8138ARM but it happened to be AD8313ARM , it is a mistake of them which took me weeks, and now I change back to the right AD8138 and I could see the waveform swing and the correct common mode level.
The only problem now is that I used a Keysight N5182B to generate some 1Mhz to 100Mhz, but I discovered that the amplitude after the AD8138 increase significantly with the freqencies increases. the single end input Vpp is 640mV, and from 100Khz to about 30Mhz, the output voltage is flat and showed correctly at 320mV Vpp for single end, but when I tuned to around 85Mhz, the single end output voltage INCREASE to 500mV Vpp. could you please advise why?
Hi,
Thank you David for the reply and finally I found this is due to the wrong chipset from our suppliers, it suppose to be AD8138ARM but it happened to be AD8313ARM , it is a mistake of them which took me weeks, and now I change back to the right AD8138 and I could see the waveform swing and the correct common mode level.
The only problem now is that I used a Keysight N5182B to generate some 1Mhz to 100Mhz, but I discovered that the amplitude after the AD8138 increase significantly with the freqencies increases. the single end input Vpp is 640mV, and from 100Khz to about 30Mhz, the output voltage is flat and showed correctly at 320mV Vpp for single end, but when I tuned to around 85Mhz, the single end output voltage INCREASE to 500mV Vpp. could you please advise why?
Hi JinoL,
Really appreciate it and it is very clear to me, and I'm working on the 500Mhz sampling and using AD9434 as the digitizer, and could you please suggest:
[1] The figure 6 and 9 shows the max gain (Cf = 0) is just <1.5db, and when at 85Mhz, the gain seems less than 1db, this will not lead to the 320mV vs 500mV difference which ask for around 2db, do you think this is reasonable?
[2] The figure 6 and 9 showed the 1pF Cf curve, what if I add just a smaller Cf, such as 0.5pf, will it provide a little bit balance on the gain and bandwidth? Although it is not normal to use a < 1pf MLCC for me.
[3] would you suggest an easy to use device such as AD8138 which has a better flatness device and also a better -3db bandwidth (for example, 400Mhz to 500Mhz).
Thanks JinoL, very helpful!!