ad1974 configuration of sampling frequency 8kHz and 16kHz

Hello tsy333,

The registers you noted for the sampling frequency ranges are used for selecting the dividers off the PLL. The PLL is not able to run very much below 32kHz fs so you must bypass the PLL and directly clock the ADC.

When direct clocking the MCLK frequency must be 512 x fs.

So some registers will no longer apply when direct clocking, like the master clock rate setting where you set it to 256 x fs or 512 x fs along with the sampling rate ranges. These are all located in the PLL and CLOCK CONTROL 0 register.

The register you need to properly set is the PLL and CLOCK CONTROL 1 register, bits 0 and 1. Both should be set to "MCLK" instead of "PLL". These are the ADC Clock Source Select and the AUXPORT Clock Source Select. Although you many not be using the AUXPORT, you should set it to the proper setting.

I am pretty sure you still have to set the ADC OUTPUT Sample rate but you will use the 48kHz setting.

I think that is all you need to do.

The part will go down to 8kHz fs and can also run at 16kHz fs but you must externally clock it with different MCLKs if you have to switch the frequency during operation. So it would be advised to mute the audio during this change

However, if it is possible to try this, I think you can setup the part with the MCLK at 512x fs for an 8kHz fs. Then if you change the ADC Sample rate from 48kHz (it will actually be running at 8kHz due to the incoming clocks) then change it to the 96kHz setting. I think this will change the internal dividers and run the ADC at 16kHz. This way you will not need the complication of two different clock sources. I would go into the lab and set this up but I will not have time to do this for a few days.

Dave T

Great thanks for your explanation.  I have done it.