# Opamp loop stabilty analysis Hi attached here is an electronic DC load circuit. I want to do a loop stability analysis for this circuit. I mean I want to know Phase margin and Gain margin for the feedback loop.

How to do this analysis? I know that I should perform AC analysis but I don't know where should I inject or add the AC signal in the loop. Should I add AC signal at A, B, or C. Also should I ground the opamp inputs? and across what points should I see the output ie bode plot for gain and phase margin?

Thanks

Santosh

Parents
• Hi Santosh,

So, if I understand you correctly, you want to analyze the stability of this system. I'll give you a few thoughts.

In General, it does not matter at which point in the loop to insert the signal source. But in your case, it doesn't make sense to add AC voltage source to point B, because the useful signal in this section of the circuit is the current and not the voltage.

If you add a voltage source to the loop, ground the non-inverting input U1. You can also send a test signal to this input instead of inside the loop as an alternative. It doesn't matter for analysis.

I think that it is most convenient to watch the results at the output of U1.

Do you have any more questions?

Regards,

Kirill

• Hi KirV

thanks for the reply. Yes, I want to analyze the stability of the system.

As you mentioned I have added an AC voltage source at point C and grounded U1 non-inverting terminal and probing at U1 output for bode plot phase margin and gain margin. The bode plot does not look correct to me i.e. there is no 0dB in the graph I mean the gain plot is way below the zero dB so how to analyze this graph then? I need to figure out what is phase margin wrt to 0dB gain. Please suggest Thanks

santosh

• Hi Santosh,

In my opinion, there is nothing strange here and the result is quite correct. I will repeat your diagram on my computer and experiment with it to better explain it to you. I will get back to you soon

Regards,

Kirill

• SDLE_latest.asc

Ok Kirill

• Hi Kirill

here is the MOSFET SiE882DF model for spice simulation you can use

.SUBCKT SiE882DF D G S
M1 3 GX S S NMOS W= 14612968u L= 0.25u
M2 S GX S D PMOS W= 14612968u L= 2.268e-07
R1 D 3 3.000e-04 TC=8.354e-03 1.404e-05
CGS GX S 4.104e-09
CGD GX D 1.912e-10
RG G GY 1.1
RTCV 100 S 1e6 TC=1.201e-04 1.184e-06
ETCV GX GY 100 200 1
ITCV S 100 1u
VTCV 200 S 1
DBD S D DBD
****************************************************************
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8
+ RS = 5.000e-04 KP = 9.470e-06 NSUB = 8.823e+16
+ KAPPA = 5.338e-04 ETA = 1.621e-05 NFS = 2.286e+11
+ LD = 0 IS = 0 TPG = 1)
***************************************************************
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8
+NSUB = 1.857e+16 IS = 0 TPG = -1 )
****************************************************************
.MODEL DBD D (
+FC = 0.1 TT = 2.615e-08 T_MEASURED = 25 BV = 31
+RS = 1.000e-03 N = 1.016e+00 IS = 8.205e-12
+EG = 1.143e+00 XTI = 2.463e-01 TRS1 = 1.000e-05
+CJO = 2.000e-09 VJ = 9.000e-01 M = 2.693e-01 )
.ENDS

Thanks

Santosh

• Hi Kirill

here is the MOSFET SiE882DF model for spice simulation you can use

.SUBCKT SiE882DF D G S
M1 3 GX S S NMOS W= 14612968u L= 0.25u
M2 S GX S D PMOS W= 14612968u L= 2.268e-07
R1 D 3 3.000e-04 TC=8.354e-03 1.404e-05
CGS GX S 4.104e-09
CGD GX D 1.912e-10
RG G GY 1.1
RTCV 100 S 1e6 TC=1.201e-04 1.184e-06
ETCV GX GY 100 200 1
ITCV S 100 1u
VTCV 200 S 1
DBD S D DBD
****************************************************************
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8
+ RS = 5.000e-04 KP = 9.470e-06 NSUB = 8.823e+16
+ KAPPA = 5.338e-04 ETA = 1.621e-05 NFS = 2.286e+11
+ LD = 0 IS = 0 TPG = 1)
***************************************************************
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8
+NSUB = 1.857e+16 IS = 0 TPG = -1 )
****************************************************************
.MODEL DBD D (
+FC = 0.1 TT = 2.615e-08 T_MEASURED = 25 BV = 31
+RS = 1.000e-03 N = 1.016e+00 IS = 8.205e-12
+EG = 1.143e+00 XTI = 2.463e-01 TRS1 = 1.000e-05
+CJO = 2.000e-09 VJ = 9.000e-01 M = 2.693e-01 )
.ENDS

Thanks

Santosh

Children
• Hi Santosh,

I applied a test signal to the non-inverting input and added an offset so that the transistors were in the linear area of operation.  The fact that the graph is not at 0 decibels should not confuse you. This will only happen if the feedback circuit transmits a signal from the U1 output to its input with a factor of exactly 1. But here, in the feedback circuit, the voltage - current conversion is performed and Vice versa, and there is an additional gain of 10 times using U2. Therefore, we have a complex dependence of the transfer coefficient of the feedback circuit on the frequency.

In order to understand whether this system is stable or not, it is enough to make sure that there is no peak on this graph. The absence of a gain peak indicates a sufficient phase margin in the loop.

It is also possible to implement more detailed and sophisticated analysis methods here, but this is more complicated. If you need this, I can probably help.

Regards,

Kirill

• Hi Kirill

Thanks for the explanation. appreciate your efforts.

i did not understand how to conclude that this system is stable or have enough margin

Santosh