AD8129 noise improvement

Hi Jayson042907,

Can you share more details about your schematic configuration? How much noise are you measuring on the AD8129 that you'd like to reduce the noise?

Regards,

Hooman

Hello Hooman,

Sorry for the late reply.

I used the AD8129 as a differential amplifier with the attenuator circuit of 4M ohms & 40k ohms.

My criteria for noise is 0.65mV but the actual noise that I measured is 1.2mV.

Do you have any idea how to reduce the noise further?

Please teach me how to calculate the noise for AD8129.

Hi Jayson,

If you convert your jpg picture to a zip file you can upload onto EZ.

Regards,

Hooman

Hi Jayson,

Regarding the JFET buffer you're trying to put together:

As I already mentioned on Sept. 17, a single transistor JFET will not function well as a DC coupled voltage follower due to non-zero VGS. That's why in this article they explain how to use two matched JFET's to eliminate this offset:

https://www.planetanalog.com/buffer-amplifier-design/

So, I recommended an off-the-shelf buffer may be the way to go.

BTW, getting 75MHz out of your 100:1 attenuator may need some careful compensation because of the resistor / trace capacitances. A stray capacitance of 0.5 fF is enough to jeopardize this frequency with 4M resistance, unless you manage to compensate properly.

Regards,

Hooman

Hello Hooman,

Do you have any idea regarding 1/f noise of AD8129?

I cannot find it in datasheet.

I already add JFET follower in my circuit but the noise becomes bigger.

Regards,

Jayson

Hello Hooman,

My zip file is already expire.

I try .rar file but still cannot upload my circuit.

Best regards,

Jayson

Hi Jayson,

You can also attach an acrobat / pdf file here, if you can convert to pdf?

Regards,

Hooman

Here is a test to see if I can attach a jpg file?

If the image of a key board shows up, then yes you can attach a jpg file a well.

Hooman

Here are the noise plots of AD8129:

The lower plot is incorrectly shown as "Current Noise Density". I've corrected it to read "Voltage Noise Intensity" instead.

Operating at up to 75MHz, per your requirement, you'd most likely not be limited by 1/f noise but rather by flat-band noise.

Regards,

Hooman

Hello Hooman,

I attached my actual circuit.PDF

Can you teach me how to compute the noise per stage?

I want to learn how to compute it and what are the parameters need to consider in design.

Thank you very much.

Best regards,

Jayson

Hi Jayson,

Here is what I did:

1. Took your circuit and simulated it with LTspice.

2. Since the AD8129 Pspice model does not include noise, I added the input referred input noise voltage, and input noise current (2 places) sources.

3. I verified your JFET amplifiers functionality using Transient Simulation.

4. I used LTspice to predict the output noise under two different conditions:

a) With your JFET buffers in place including the 100:1 attenuator.

b) With your JFET buffers bypassed and the 100:1 attenuator tied to AD8129 inputs.

I found that with JFET buffers in place, I measure a much lower output noise density (371nV/RtHz) vs. the case where the 100:1 attenuator is tied to the AD8129 inputs (675nV/RtHz).

I've shown the noise density plots for these two cases below for comparison:

Here are the simulation files included:

ad8129 EZ JFET Noise LTspice 10_3_19.zip

So, simulations show the opposite of what you found; the JFET buffers do reduce noise. In fact, the simulation difference is exactly the 1pA/RtHz device noise * 40k * Gain, on each input.

There is an improvement in bandwidth using simulation with the JFET buffers, which may be responsible for you measuring higher noise? Please double check in case you're measuring the noise using time-domain?

Regards,

Hooman

Hello Hooman,

 May I asked if the simulation includes the noise generated by the FET (LS5911) & PMBT2222A?

 Is it possible that the noise is caused by the transistor?

 My set-up in measuring noise is I short the (+/-) inputs and measured the output by the Oscilloscope (with BW limit = 20MHz). 

Best regards,

Jayson

Hello Hooman,

 May I asked if the simulation includes the noise generated by the FET (LS5911) & PMBT2222A?

 Is it possible that the noise is caused by the transistor?

 My set-up in measuring noise is I short the (+/-) inputs and measured the output by the Oscilloscope (with BW limit = 20MHz). 

Best regards,

Jayson

Hi Jayson,

To answer your questions:

1. Discrete Noise: Yes, the simulation includes all noise sources, including the JFET and the NPN. However, you're dominated by the 40kohm resistor thermal noise (26nV/RtHz) at the Source of the JFETs.

2. Xsistor Noise: No, the JFET noise (4nV/RtHz) does not factor into this, again because the 40kohm input attenuator noise dominates at 26nV/RtHz. Nor does the NPN noise because there is no gain from the NPN base to its collector (because the collector is looking to the low impedance of the JFET source).

3. Time-Domain Measurement: With a 20MHz bandwidth, LTspice shows JFET buffered output noise of 1.47mV_RMS (or 9.7mVpp assuming 6.6x factor). That's vs. 780uV_RMS for the 100:1 directly interfacing the AD8129!

The main reason for what you're measuring can be seen in the plot below where with the JFET's buffers in place, you're extending your circuit's BW from 670kHz to 18MHz! The most likely reason for the low bandwidth with the 100:1 attenuator directly interfacing with AD8129 is the input capacitance of the AD8129 lowering your frequency response. With the JFET buffers in place, you've eliminated this RC pole because of the lower Gate capacitance of the JFET's.

So, the JFET circuit will have higher bandwidth and thus will measure noisier on the scope. For a true comparison, you must roll-off the bandwidth of the JFET setup to match the un-buffered setup.

Regards,

Hooman