I used AD8129 as a differential amplifier in my project.
My specifications are meet the criteria except for NOISE.
Is there any way to improve the noise for AD8129?
Please teach me how to improve the noise of AD8129.
Can you share more details about your schematic configuration? How much noise are you measuring on the AD8129 that you'd like to reduce the noise?
Sorry for the late reply.
I used the AD8129 as a differential amplifier with the attenuator circuit of 4M ohms & 40k ohms.
My criteria for noise is 0.65mV but the actual noise that I measured is 1.2mV.
Do you have any idea how to reduce the noise further?
Please teach me how to calculate the noise for AD8129.
The AD8129 output RMS noise is going to have the following components:
1. AD8129 input referred voltage noise: 4.6nV/RtHz * Gain
2. Your attenuator noise:
a) 4M resistor: 257nV/RtHz --> 40k/(4Meg+40k) * 257nV/RtHz = 2.55nV/RtHz (at AD8129 input)
b) 40k resistor: 25.7nV/RtHz --> 25.7nV/RtHz (at AD8129 input)
These will be gained by the AD8129 gain and appear at the output.
3. AD8129 input referred current noise: 1pA/RtHz * 40k * Gain = 40nV/RtHz * Gain
4. REF and FB noise (1.6pA/RtHz): These will be insignificant compared to other noises
Therefore, the AD8129 input current noise will be dominant, followed by the 40k resistor thermal noise. The AD8129 input voltage noise is far less dominant in this situation.
So, the most effective way to minimize the noise is to reduce the impedance looking into the input(s) of the AD8129 so that the input bias current does not flow through the attenuation resistors (40M, and 40k).
Can you add a low noise, high impedance buffer after the attenuator and before the AD8129? This way the high input bias current of the AD8129 is not sourced through the attenuator impedance of around 40kohm and would instead be supplied by the low noise buffer.
I forgot to mention.
Of course lowering the values of your attenuation is another way to improve the AD8129 output noise, if the buffer after the attenuator idea above is not feasible.
If your application allows a much lower impedance 100:1 attenuation, like 100k and 1k, the noise will be lower by about 10x factor, as described below:
1) 1k noise: 4.07nV/RtHz
2) AD8129 input referred current noise RTI: 1pA/RtHz * 1k= 1nV/RtHz
3) AD8129 input referred voltage noise RTI: 4.6nV/RtHz
So now, you'd be limited by the AD8129 voltage noise and not by the attenuator thermal noise or the AD8129 input current noise flow through the attenuator impedance.
The noise reduction will be from ~40nV/RtHz to ~4.6nV/RtHz when you drop the attenuator resistors by a factor of 40x from 40k to 1k.
Thank you for the suggestion.
I prefer your first suggestion to add a buffer after the attenuator. Because the attenuator is already fixed and the only thing need to change is the voltage gain(Rg & Rf) of the AD8129.
I will use a source follower FET transistor configuration as a buffer.
Do you think it is good idea? Please give me advice.
It is my first time to design a project regarding the AD8129 application.
Thanks & best regards,
Regarding a JFET follower before the AD8129 to reduce AD8129 input bias current induced noise:
I assume you have a DC coupled signal path.
To implement such a discrete JFET buffer when you're DC coupled, I think you'd have to get creative with matching JFET VGS, etc. as described in this article:
This may not be a practical approach.
You may be better off just using a low noise, low input bias current integrated buffer like ADA4891-1 or ADA4610-1 instead to avoid having to deal with the DC offset problem.
Hope this helps.
Regarding AD8129 and your need to reduce noise:
If you're attenuating the input signal, are you sure AD8129 is the right part to use? AD8129 is only stable for gains of 10V/V or higher. AD8130 can be used at a gain of 1V/V. So, I can't quite understand why the need for attenuation if you're running the AD8129 at 10x gain or higher?
Furthermore, do you know what signal bandwidth you need? I'd guess that that your 100:1 attenuator (4M, 40k) is band-limited to 1MHz or less. If so, you'd probably benefit from reducing the bandwidth you get from AD8129 (or AD8130?). I've done that in the zip file attached below where a 5pF cap across RF has reduced the overall bandwidth to around 1MHz to reduce the output noise. You could manipulate the circuit yourself to see the effect.
AD8129 LTspice response 9_18_19.zip
Note: The AD8129 pspice model from the web, which I've imported into LTspice, does not model the device's noise as shown in the model's text / comments lines.
I have a question regarding JFET follower. JFET follower has a unity voltage gain so, Vin is almost equal to Vout.
But in my actual experiment, Vin is not equal to Vout. When my Vin1 = 0.2V , the Vout1 = 1.201V. The actual Vgs value = -1.01V. While Vin2 = 0.0V, the Vout2 = 1.01V. Therefore, Vout = Vin - Vgs.
Is it correct? How can I make Vin = Vout?
I cannot upload the picture of my circuit. I hope you understand my circuit.
I used LS5911 IC JFET. I connect +9.5V at the Drain ( pin 6 & pin 2). I input Vin1 = 0.2V to LS5911 pin 7 and Vin2 = 0.0V to LS5911 pin 3. I connect RS = 2K ohms to the LS5911 pin5.
Then, I connect a current source (BJT) at the end of RS resistor.
I used PMBT2222A transistor as a current source. I used RB = 51K connected to the ground at the other end. I connect LED (Vf = 1.2V) to PMBT2222A pin 1 and the other end is connected to -9.5V supply. I connect RE = 500ohms to PMBT2222A pin 2 and the other end of the RE is connected to -9.5V supply.
My +Vin of AD8129 is connected to LS5911 pin 1 while the -Vin of AD8129 is connected to LS5911 pin 5.
Thank you very much for your suggestion.
My BW requirement is 75MHz.
I will try it after I finish my experiment in JFET follower.
I'm still debugging the JFET follower.
If you convert your jpg picture to a zip file you can upload onto EZ.
Regarding the JFET buffer you're trying to put together:
As I already mentioned on Sept. 17, a single transistor JFET will not function well as a DC coupled voltage follower due to non-zero VGS. That's why in this article they explain how to use two matched JFET's to eliminate this offset:
So, I recommended an off-the-shelf buffer may be the way to go.
BTW, getting 75MHz out of your 100:1 attenuator may need some careful compensation because of the resistor / trace capacitances. A stray capacitance of 0.5 fF is enough to jeopardize this frequency with 4M resistance, unless you manage to compensate properly.