LT1011 Comparator SPICE Model

Hi SSneed198,

Attach here is the spice model for the LT1011. This a generic model that was validated and proven to work in LTSpice. If you encounter any problems, or if you have any questions regarding the model just let me know!

Thanks,

Donnie

* Copyright (C) Linear Technology 09/13/2006. All rights reserved.
* Pinout (same as IC): GND IN+ IN- V- BAL STROBE OUT V+
.SUBCKT LT1011 1 2 3 4 5 6 7 8
DIN3 4 2 DIN
DIN4 4 3 DIN
RG1 23 0 4.5E6
GTRFOC 0 24 VALUE={MAX(0,5*tanh(V(23)))}
RTRFOC 24 0 1
CTRFOC 24 0 1E-8
ITYP 8 4 1.5E-3
DV1 56 23 DVLIM
DV2 56 0 DVLIM
GIN 0 23 VALUE={11*tanh(V(3,2)+3E-4)+1.78E-6*((((V(2)+V(3))/2)-V(4)))}
IB1 0 2 15.2E-9
IB2 0 3 15E-9
ROUT 8 7 1E9
GSTR 23 0 VALUE={10+10*TANH(100*(V(55,6)-0.05))}
CG1 0 23 2E-9
RB1 55 5 300
RB2 0 55 100
GBAL 0 23 VALUE={-10*V(5,6)}
RB3 6 55 300
GB3 0 55 VALUE={0.01*(V(8)-0.125)-4.4E-6*V(24,1)}
MOUT 11 24 1 1 NOUT
GNO 0 24 1 0 1
CEM 1 4 1E-10
CIN1 2 8 3E-12
CIN2 2 4 3E-12
CIN3 3 8 3E-12
CIN4 3 4 3E-12
COUT 7 1 5E-11
GVESAT 24 0 VALUE={10+10*TANH(5*(V(1,8)+2))}
GILIM 7 11 VALUE={MIN(5E-2,10*V(7,11))}
RDUM1 7 11 1E11
.MODEL NOUT NMOS(KF=0 KP=0.02 VTO=0.1 RD=7)
.MODEL DVLIM D(BV=3 IS=1E-18 KF=0 RS=0 XTI=0)
.MODEL DIN D(KF=0 RS=0)
.ENDS LT1011

Hi Donnie,  thanks for the model.  It works fine when driving a resistive load tied to +Vcc, however I think I might have a problem with my battery test circuit driving a resistive load from the GND pin as shown in the third figure of page 11 of the data sheet.  As I sweep the non-inverting input from -9V to -3V with a DC Sweep, the current through the load resistance remains at 0A.  Do you have any idea where my model went wrong?  Is it possible that the LT1011 model hasn't been verified for this use case?

Hi Donnie.  I found the reason why it wasn't simulating.  PSPICE doesn't seem to like two independent circuits on the same schematic sheet.  Once I created the design on a separate schematic, the design simulated properly.  Thanks again.  Regards.