I've been modeling the LT6600-10 in the below circuit and the SPICE model outputs Vocm imbalance of +/- 20 mV. Is this correct and is there a way to mitigate it?
40 uA bias current times big R times gain of 100 should give you volts, not millivolts.
LTSpice is telling you what the real silicon would probably do.
Ah, I see I put my input Rt on the wrong side of the coupling cap. Thanks.