I need to understand how Zero-IF receiver architecture blocker signals are taken care. For example :
According to 3GPP at 60MHz offset from operating frequency edge there is blocker power level of CW -15dBm and consider a quadrature demodulator or transceiver whose max input power is -10dBm.
RF front end gain = 35dB.
So blocker signal power = -15dBm + 35 = +20dBm.
If external Band pass filter provides the rejection of 10dBc at the offset 60MHz, the blocker power level = +10dBm.
If this blocker signal passes through quadrature demodulator or transceiver :
1.Does this blocker signal saturate my ADC or is there a technique/method involved to resilient the blocker signal.
2. OR blocker frequency should be eliminated or rejected via external band pass filter.
I need to know is it possible blocker signals are rejected or eliminated in the quadrature demodulator or transceiver so that external band pass filter can be relaxed.