I`d like to know the maximum value of IDRVDD for AD9251. the data sheet page26 indicated as below: IDRVDD = VDRVDD × CLOAD × fCLK × N where N is the number of output bits (30, in the case of the AD9251), the clock of my design is 4MHz, if following this formula, if assumed the CLOAD is 5pF, IDRVDD_max is about 3.3V*5pF*4MHz*30=1.98mA, am I right? would you please confirm this calculated result?
in addition there had the description "In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 54). " what is the scenario of using a single-ended 1.8 V CMOS signal for the CLK input?
please answer my above two questions, thanks for your support!
add some detailed information.
[edited by: ShawnTiger at 6:16 AM (GMT -4) on 18 Apr 2022]