LTspice ADA4528-2 time vs frequency, response conflict

As you can see we have excellent frequency response:

but time response is really not acceptable:

Why this has been happened?

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  • +1
    •  Analog Employees 
    •  Super User 
    on Jan 13, 2021 1:11 AM in reply to mohammadsdtmnd

    Hi mohammadsdtmnd,

    Your circuit suffers from a lack of Phase Margin. You can simulate this using the technique outline here:

    https://www.analog.com/en/education/education-library/videos/5579254320001.html

    I've done that and I see a negative phase (-54deg.) when the loop gain (magnitude plot) crosses 0dB. Nominally, you'd need > 50 deg. of phase margin to avoid instability which is what you see in the transient analysis:

    Phase margin is the phase reading where the plot magnitude shown crosses 0dB.

    A major culprit of lack of phase margin (excessive phase shift around the loop) is the large value cap C14 (6.8nF). Eliminating C14 improves your phase margin to 7deg. which is still not enough.

    You may want to go back to how you generated this filter solution and take another look at the suggested components which seem to create a non-standard, and unstable filter topology and re-evaluate.

    Here is the phase margin analysis LTspice simulation for reference:

    Line receiver_V3 EZ Phase Maring 1_12_21.asc

    Regards,

    Hooman

  • Hi human

    Thanks a lot, but you've deleted the half of circuit, is that right? I think intuitively that will only affect CMRR and here is not important although maybe help gain to raise 3dB. I've found TI Stability compensation technique and I will read it to compensate my circuit, and again thanks a lot.

    with highest regard

  • 0
    •  Analog Employees 
    •  Super User 
    on Jan 24, 2021 12:20 AM in reply to mohammadsdtmnd

    Hi  mohammadsdtmnd,

    Yes, that's correct.

    I eliminated the 1/2 of circuit connected to the non-inverting input of ADA4528-2. That portion has no effect on the Loop Gain or Phase Margin and won't affect stability at all because it is not involved with the feedback path.

    Regards,

    Hooman

  • Hi again

    I've just confused, when the simulator tells that everything ok, or the frequency analysis is perfect, there is no spike in anywhere. why time response has got wrong. when phase at 7khz is 0 the output must amplify the frequency but you can see that is is bounded to certain nice value. Academically and intuitively why the response goes wrong?! Edit: I have seen spike in case when we use open loop technique but this is not our actual case.

  • 0
    •  Analog Employees 
    •  Super User 
    on Feb 4, 2021 8:58 PM in reply to mohammadsdtmnd

    Hi again,

    I've seen this before where AC response simulation may indicate all-is-good with a circuit whilst transient simulation says otherwise. There may be clues in the otherwise "good" AC response as well, but I'm not an expert to know and identify those. So, I always perform both these simulation which of course is still no-guarantee that the final circuit is perfect either. Bench characterization is essential in spite of simulation.

    Regards,

    Hooman