LTspice ADA4528-2 time vs frequency, response conflict

mohammadsdtmnd on Dec 24, 2020

As you can see we have excellent frequency response:

but time response is really not acceptable:

Why this has been happened?

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Hooman
Jan 13, 2021 in reply to mohammadsdtmnd +2 verified
Hi mohammadsdtmnd,

Your circuit suffers from a lack of Phase Margin. You can simulate this using the technique outline here:

https://www.analog.com/en/education/education-library/videos/5579254320001.…
mohammadsdtmnd Dec 31, 2020 in reply to dcruz +1

When holiday will finishes? I want to send my layout to manufacturer.
Hooman
Jan 2, 2021 in reply to mohammadsdtmnd +1
Hi mohammadsdtmnd,

I see that you're operating the ADA4528-2 with single supply. If you switched to dual supply (+/-2.5V), does that help resolve your issue with the step response? Is this something you…

0 dcruz

on Dec 26, 2020 7:14 AM 8 months ago
Hi,

Responses may be delayed, because of the holidays. I'll get back to you as soon as possible.

Thanks,

Donnie
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0 mohammadsdtmnd on Dec 31, 2020 6:11 AM 8 months ago in reply to dcruz

When holiday will finishes? I want to send my layout to manufacturer.
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0 Hooman

on Jan 2, 2021 6:15 AM 8 months ago in reply to mohammadsdtmnd
Hi mohammadsdtmnd,

I see that you're operating the ADA4528-2 with single supply. If you switched to dual supply (+/-2.5V), does that help resolve your issue with the step response? Is this something you can try?

Also, it'd help if you attach your LTspice simulation file (*.asc) to this post. You can do so under the "Insert" menu.

Please let me know.

Thanks.

Regards,
Hooman
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0 mohammadsdtmnd on Jan 12, 2021 8:48 PM 8 months ago in reply to Hooman

Hi Homan!
Thanks for your responses.
Even double supply doesn't help. The simulation is Here.

With highest regards.
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+1 Hooman

on Jan 13, 2021 1:11 AM 8 months ago in reply to mohammadsdtmnd
Hi mohammadsdtmnd,

Your circuit suffers from a lack of Phase Margin. You can simulate this using the technique outline here:

https://www.analog.com/en/education/education-library/videos/5579254320001.html

I've done that and I see a negative phase (-54deg.) when the loop gain (magnitude plot) crosses 0dB. Nominally, you'd need > 50 deg. of phase margin to avoid instability which is what you see in the transient analysis:

Phase margin is the phase reading where the plot magnitude shown crosses 0dB.

A major culprit of lack of phase margin (excessive phase shift around the loop) is the large value cap C14 (6.8nF). Eliminating C14 improves your phase margin to 7deg. which is still not enough.

You may want to go back to how you generated this filter solution and take another look at the suggested components which seem to create a non-standard, and unstable filter topology and re-evaluate.

Here is the phase margin analysis LTspice simulation for reference:

Line receiver_V3 EZ Phase Maring 1_12_21.asc

Regards,

Hooman
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