I have 0V to 5V signal on VCOM=2.5V where op-amp circuit (it active filter, gains, etc) sits between 0V and 5V. The signal is up to 100Hz B/W and it it not DC.
In case of VCOM wiggles, the signal would wiggles as common mode. The VCOM is driven by low impedance op-amp (+/-10mA drive).
I would like to attach these signal to the AD7988-1 which is 16 bits SAR (I'm looking into AD7732 later based on SD)
IN- connect to VCOM (2.5V)
IN+ connect to signal (OP2177 op-amp output) of +/-1.5Vpp (1V to 4V)
I connect AD7988-1:
VREF = 4.096 (ADR364),
VDD = 2.5V (ADR361)
and VIO = 3V3 for SPI bus, sampling at 1KSPS on SPI bus. The AD7988-1 has internal clock for conversion processing.
My concern that
(1) The impedance of the IN+ and IN- is low but datasheet quoted that for high speed
(2) The impedance may be inbalance, not clear on datasheet
(3) The common mode rejection between +IN and -IN is not clear on datasheet
I'm trying to figure out what to expect in performance based on above circuit, the datasheet is rather limited in details.
Has anyone used this device based on above configuration based on low sample rate, is common mode rejection any good (before I get to instrument amp).
How to estimate actual impedance for lower sample rate, I can have 10nF cap between IN+ and IN- so it handle transient operation while sampling.