Single-ended to differential amplifier at ppm level - Questions on DN1032

Hello everyone,

It's been a while since I'm doing research on ADC acquisition close to 10 ppm level.

For the short story:
I'm currently design a voltmeter with high precision.
I have almost all my acquisition chain in my architecture, except one:  the single-ended to differential amplifier (needed for the ADC).
I'm twisting my neurons about this stage which can fly away the linearity of the ADC.

I found the example from the datasheet of the LTC2442 (p.28) and the Design Note 1032 (DN1032) which explains and answers to my problematic by a similar solution: create the complementary signal with an inverting amplifier (and centering it, in passing).

However, I still have 2 interrogation on the given schematics (I am refering to the DN1032):

Question 1
The inverter amplifier which creates the -180° phase signal has a gain fixed by 2 resistors R5 and R6 (more the additional resistor R4).
There is no mention anywhere of the effect of the drift of this gain.
For me, it will impact directly the negative signal and imbalance the input of the ADC. Moreover, I don't see how this gain can be calibrated.
The DN-1032 explains that a quad matched resistor is needed to divided the signal precisely after the amplifier, but nothing for the gain of the inverter.
Note: The centering of the differential signal has less impact on the result of the ADC. So, I don't talk about the resistors R1 and R2. 


Question 2
The inverting amplifier creates a shift phase (a delay) compare to the direct positive signal.
For the very low frequency, it will be good but for higher frequencies (>10kHz), it's can be a problem.
On solution can be to minimize the delay with an active compensation into the feedback of the inverting amplifier.
Another solution will be to use a fully differential amplifier which by design ensure a symmetry but they are often design to AC and less concern about DC.
In the book "The Art of Electronic", it shows different ways to create a differential stage but they used a lot of a resistor (more than a quad which are not available in network).
However, I wonder if the fact to choose a truly differential stage by design will improve the precision because it wills add more components and with that more problems...
 What will be your point of view or your approach?


More details on my project:

For now, I have in mind to use for the main ADC: LTC2442 (or LTC2376-20). Principally for their linearity and their stability.
I expect 18 bits absolute precision after calibration and for low frequency (<1kHz).
In front-end, I will use Jfet famplifiers op-amp (ADA4625) or, if I success to buy it, a dual jfet monolithic to build a discrete Jfet composite amplifier.


Thank you for your reading, Best regards,

  • +1
    •  Analog Employees 
    on Aug 12, 2019 4:59 PM

    In DN1032, the inverting amplifier U3, acts merely to keep the common mode voltage within the required Vref/2 +/-100mV. As long as it does this, its absolute accuracy is not necessary. The circuit of DN1032 is designed primarily for DC applications. If you look at the demo manual for DC2135A which is based on the circuit of DN1032 you will see that performance starts to degrade with input frequencies above a few hundred Hertz. If you are looking for a solution that will work at higher frequencies, I suggest you consider the ADA4945 fully differential amplifier.

  • Thank you Mr. G.Hoover for your answer (And your note design by the way),

    Sorry for the time I take to answer. I take time to understand because I didn't feel at the first time the effect of R5/R6
    because I just stop at the enter of the ADC and I not push forward.
    I detail my calculs below if it can help other people.

    First step with U3 :
      V_u3_out = Vref - Ain/2

    Then U5 does a division by 2 of Ain which results :
      V_u1_in+ =   Ain/4 + Vref/2
      V_u1_in- = - Ain/4 + Vref/2
    So, if the gain of U3 is not exactly 1/2 (caused mismatch and drift of R5 and R6), we have:
      V_u3_out = Vref - Ain*(R5/R6)
               = Vref - Ain*Beta     with Beta = R5/R6 = ~1/2
    Therefore after U5, we have:
      V_u1_in+ =     (Ain/2)*(1-Beta) + Vref/2  
      V_u1_in- =   - (Ain/2)*Beta     + Vref/2

    In the ADC, we have:
      V_u1_in = V_u1_in+ - V_u1_in-
              = (Ain/2)*(1-Beta) + Vref/2 - (- (Ain/2)*Beta     + Vref/2)
              = (Ain/2)*(1-Beta) + Vref/2 + (Ain/2)*Beta - Vref/2
              = (Ain/2)*(1-Beta) + (Ain/2)*Beta
              = (Ain/2)
    So, the mismatch of R5/R6 disappear.
    Very clever!