Greetings,
I'm customizing the FPGA logic in a Pluto Rev C. I have disabled the TDD in the AD9361 to save FPGA resources; this works. I notice there is an AXI target axi_tdd_0/tdd_core which consumes some logic resources. Can someone recommend how to safely remove this? I considered simply tie-ing off the AXI target interface to always return 0's. However, I suspect there is a more complete solution where I tell the processing system that this device is no longer here?
Better yet, I would like to use this target destination as my own AXI interface, but that is beyond the scope of my question and I think has been answered before. For now I would just like my FPGA resources back.
Regards,
Steve