Greetings,
I'm developing some HDL on the programmable-logic (PL) side of the PLUTO (rev C). I have a working GPIO input that I wish to use as a sync. I also have working code where I can get between the AD9361 and the CPACK module before going to the ADC DMAC.
I had planned on masking the write enable after a RX DMA request until my sync signal was asserted (typically within 10mS). I am using the Python bindings with adi lib and IIO to read the RX data.
import adi sdr = adi.ad9361(uri='ip:192.168.2.1') data = sdr.rx()
The problem I have is that the python command "data = sdr.rx()" times out due to my holding off of write enable even for a mS. I doubt that this timeout is a function of the DMAC hardware; I don't expect it has a wait limit on the AXI bus. Therefore I am guessing that this time-out limit is specified somewhere in the software stack.
My question is: Can someone advise me where in the Python, IIO or on-device linux/drivers I can find the code where the timeout is specified? I've been digging and so far haven't made much progress.
An alternative would be for me to understand how to get a buffer address similar to that which the DMA uses (I'm guessing it's an AXI address directly into the DDR?). What would the software look like to reserve the buffer for the RX data, but not start the DMA to fill it? Rather once I have the buffer, I can make an AXI device to copy the RX data on trigger into the memory. Then I can read the buffer (from Python) at my leisure and release it.
Thanks for any help or suggestions.
Regards,
Steve
