Pluto SDR AXI Quad SPI - Used only for boot?

Hi,

I think you are confusing IIC with QSPI. This are two separate interfaces.
You should not temper with the QSPI one.
The IIC pins are available and you can add additional functionality.
https://wiki.analog.com/university/tools/pluto/devs/controlling_gpios

Andrei.

Andrei,

Thank you. I see I did conflate IIC and SPI in my original post, I've since edited it.

However I still have my original question: if the phaser_enable mode signal can change this particular SPI (from PL that ultimately connects to L10P, L12N, L24N) is it OK to add another mode signal to change it to something else?

I confirmed this in the schematic. (I should have done this before posting)
https://wiki.analog.com/_media/university/tools/pluto/hacking/plutosdr_schematic_revb.pdf

Page 6, BANK 34, indicates IO_L10P_T1_34 connects to PL_GPIO0 trace, and only to L10P. (And as far as I see, nothing else.) In the Verilog block design, some portion of the AXI Quad SPI (axi_spi)  is shared via the phaser_enable signal. One pin for example, the spi_sdo_o connects in the wrapper to pl_spi_mosi, which is shared with pl_txdata via the phaser_enable as pin PL_GPIO0. This matches the first line of the first table in the link you posted.

So, if the phaser_enable mode signal can change the SPI is it OK to add another mode signal? 

For what it's worth. I dug into the SPI used for FLASH. DQ0 of QSPI Flash connects to PS_MIO02_500_QSPI0_IO0 trace, to XC7Z010-1CLG225C input pin A8, PS_MIO2_500. From system_constr.xdc I see this connected as port fixed_io_mio[2]. This fixed_io_mio connects to the sys_ps7 MIO interface. I believe the SPI mentioned for BOOT is PS (system) - a different SPI than the axi_spi that is PL (programmable logic). This would be good to be confirmed by someone if they know for sure. Seems the original post (Pluto SDR AXI Quad SPI ) could be clarified?

Thanks again,
Steve

skorson said:

However I still have my original question: if the phaser_enable mode signal can change this particular SPI (from PL that ultimately connects to L10P, L12N, L24N) is it OK to add another mode signal to change it to something else?

skorson said:

So, if the phaser_enable mode signal can change the SPI is it OK to add another mode signal? 

Yes.
It is up to you. The SPI, was added there just to help users. SPI is one of the most used interfaces. If you don't used it you can remove it.
But you can also add a 3'rd 4'th and so on option(s).

The axi_spi is included as a software SPI, it can be used from the Linux user space.
https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/zynq-pluto-sdr-revc.dts#L64-L85

skorson said:

For what it's worth. I dug into the SPI used for FLASH. DQ0 of QSPI Flash connects to PS_MIO02_500_QSPI0_IO0 trace, to XC7Z010-1CLG225C input pin A8, PS_MIO2_500. From system_constr.xdc I see this connected as port fixed_io_mio[2]. This fixed_io_mio connects to the sys_ps7 MIO interface. I believe the SPI mentioned for BOOT is PS (system) - a different SPI than the axi_spi that is PL (programmable logic). This would be good to be confirmed by someone if they know for sure. Seems the original post (Pluto SDR AXI Quad SPI ) could be clarified?

Thank you for bringing this to my attention.
I will add a clarification to that thread.

Andrei