Hello, I've modified Pluto SDR fpga project and generated a new bitstream in Vivado. Now I'm trying to update fpga with the new bitstream.
I looked through https://wiki.analog.com/university/tools/pluto/devs/fpga and https://wiki.analog.com/university/tools/pluto/users/firmware to find any info about fpga update.
I have XILINX Platform Cable USB II (https://www.mouser.com/ProductDetail/AMD-Xilinx/HW-USB-II-G?qs=rrS6PyfT74cTrO3YL49xhw%3D%3D ).
Do I still need to purchase ADALM-UARTJTAG ? I saw a few questions in the Engineering Zone where they connected Xilinx USB II directly to Pluto SDR
I tried connecting XILINX Platform Cable USB II to "0.05 PITCH JTAG AND UART CONNECTOR" on Pluto (see pluto schematic)
XILINX PLUTO 0.05 PITCH JTAG
TMS pin 2 (JTAG_TMS)
TCK pin 4(JTAG_TCK)
TDO pin 6 (JTAG_TDO)
TDI pin 8
GND pin 7&9 (GND)
VREF pin 10 (1V8) (I tried with this and without this, the same error)
I get the following error in vivado
[Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Xilinx/00001eec2cca01.
Check cable connectivity and that the target board is powered up then
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
1. Am I connecting the Xilinx programmer correctly, if not what should be changed?
2. Should I use VREF and HALT/INIT/WP wires on Xilinx Platform Cable USB II? If yes, then how?
3. should I power on Pluto (PC usb or power usb)? I tried no poser, PC usb, and power usb, non of them worked.
4. There is P1 jtag 10 pin connector, and the following holes around it GND, TCK, RMS, RX, TX, JTAG_BOOT, TDI, TDO . Should I use 10 pin header or the holes?
Thanks
