I am trying to flash adalm pluto using Xilinx Platform cable and reference HDL Design from github.
I created an image file using Vitis 2022.2 named boot.bin. Now I want to flash this image to Adam pluto memory. The flashing process is completed but can't be seen with putty I was trying to test a "Hello World" code for simplicity. Is there something missing because when I debug and run the same application program, I can see the "Hello World" message via uart connection in putty. Do I also need to update the firmware in order to run the program automatically every time it is plugged in to power. Here are some screenshots from the Vitis. It can be seen that the flashing process is completed successfully if I dont click "Blank check after erase and Verify after flash".
I reviewed the firmware update files from analog devices adalm pluto wiki but didn't understand if it is necessary because I can flash the image succesfully from the vitis but can't see the "Hello World" message.
****** Xilinx Program Flash
****** Program Flash v2022.2 (64-bit)
**** SW Build (by xbuild) on 2022-10-13-12:09:36
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Connected to hw_server @ TCP:127.0.0.1:3121
Target not specified. Selecting target_id 4 (arm_dap) by default.
Retrieving Flash info...
Initialization done
Using default mini u-boot image file - /tools/Xilinx/Vitis/2022.2/data/xicom/cfgmem/uboot/zynq_nor.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
U-Boot 2022.01-00146-g0526f91 (Jul 27 2022 - 03:10:20 -0600)
Model: Zynq CSE NOR Board
DRAM: ECC disabled 256 KiB
WARNING: Caches not enabled
Flash: 0 Bytes
Loading Environment from <NULL>... OK
In: dcc
Out: dcc
Err: dcc
Zynq>
Performing Erase Operation...
protect off E2000000 E211FFFF
Error: start and/or end address not on sector boundary
Zynq> erase E2000000 E211FFFF
Error: start and/or end address not on sector boundary
Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Program Operation...
protect off E2000000 E211FFFF
Error: start and/or end address not on sector boundary
Zynq> 0%...cp.b FFFC0000 E2000000 10000
Zynq> cp.b FFFC0000 E2010000 10000
Zynq> cp.b FFFC0000 E2020000 10000
Zynq> cp.b FFFC0000 E2030000 10000
Zynq> cp.b FFFC0000 E2040000 10000
Zynq> cp.b FFFC0000 E2050000 10000
Zynq> cp.b FFFC0000 E2060000 10000
Zynq> cp.b FFFC0000 E2070000 10000
Zynq> 50%...cp.b FFFC0000 E2080000 10000
Zynq> cp.b FFFC0000 E2090000 10000
Zynq> cp.b FFFC0000 E20A0000 10000
Zynq> cp.b FFFC0000 E20B0000 10000
Zynq> cp.b FFFC0000 E20C0000 10000
Zynq> cp.b FFFC0000 E20D0000 10000
Zynq> cp.b FFFC0000 E20E0000 10000
Zynq> cp.b FFFC0000 E20F0000 10000
Zynq> 100%
cp.b FFFC0000 E2100000 4D88
Zynq> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 61 sec.
Flash Operation Successful
...
If I flash program when it is configured like selected buttons which are "blank check after erase" and "verify after flash", program fails and gives the following error and I can't erase the previous content.
****** Xilinx Program Flash
****** Program Flash v2022.2 (64-bit)
**** SW Build (by xbuild) on 2022-10-13-12:09:36
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Connected to hw_server @ TCP:127.0.0.1:3121
Target not specified. Selecting target_id 4 (arm_dap) by default.
Retrieving Flash info...
Initialization done
Using default mini u-boot image file - /tools/Xilinx/Vitis/2022.2/data/xicom/cfgmem/uboot/zynq_nor.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
U-Boot 2022.01-00146-g0526f91 (Jul 27 2022 - 03:10:20 -0600)
Model: Zynq CSE NOR Board
DRAM: ECC disabled 256 KiB
WARNING: Caches not enabled
Flash: 0 Bytes
Loading Environment from <NULL>... OK
In: dcc
Out: dcc
Err: dcc
Zynq>
Performing Erase Operation...
protect off E2000000 E211FFFF
Error: start and/or end address not on sector boundary
Zynq> erase E2000000 E211FFFF
Error: start and/or end address not on sector boundary
Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Blank Check Operation...
0%...cp.b E2000000 FFFC0000 8000
Zynq> cmp.b FFFC0000 FFFC8000 8000
byte at 0xfffc0000 (0x0) != byte at 0xfffc8000 (0xff)
Total of 0 byte(s) were the same
Zynq> INFO: [Xicom 50-44] Elapsed time = 4 sec.
Blank Check Operation unsuccessful. The part is not blank.
ERROR: Flash Operation Failed
