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AD9363 DDR3 Lines

Category: Hardware


I'm working on implementing AD9363 on my pcb, and I came across the open source layout file for PlutoSDR. Looking at the DDR3 lines, I noticed that the data lines are not length matched. Is there a specific reason for this? is the clock slew rate low enough to gaurantee clocked edges won't get jeopardized? Would appreciate any inputs on this.