By using github adalm-pluto hdl files, we built the fpga blocks of vivado. Now we want to wrap the design (Create HDL Wrapper) so that we can use the .xsa file in vitis or sdk. Even though we can export the hardware with bitstream, we can't add the file in SDK platform. How can we solve this issue?
travisfcollins - Moved from Design Support AD9361/AD9363/AD9364 to Virtual Classroom for ADI University Program. Post date updated from Tuesday, February 20, 2024 9:47 PM UTC to Tuesday, February 20, 2024 10:26 PM UTC to reflect the move.
travisfcollins - Moved from Design Support AD9361/AD9363/AD9364 to Virtual Classroom for ADI University Program. Post date updated from Tuesday, February 20, 2024 10:26 PM UTC to Tuesday, February 20, 2024 10:26 PM UTC to reflect the move.
By using github adalm-pluto hdl files, we built the fpga blocks of vivado.
Are you using the standard HDL flow that is documented for ADI supported reference designs?
-Travis
Yes, we're using ADI supported reference designs, we just want to export the .xsa file and continue with vitis or sdk so that we can use the adalm pluto standalone. In the vitis part, it says that there are no directories in the workspace. SDK doesnt even allows us to add the .xsa file that we exported from vivado.
Our goal is to use adalm pluto standalone as I said. We're trying to build ofdm and frequency hopping features. Can you also suggest how we should proceed as in which application should we use to build this features. Can we use the verilog part in vivado or high level synthesis (C programming in vitis or sdk)?
Furthermore is there any chance you can explain step by step including how can we compile and load to adalm pluto?
The default Pluto HDL project will create an xsa automatically. Are you able to find it?
There are no specific guides for Pluto and no-OS. However it’s really no different than any other AD9361 projects so you can start with these guides https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/baremetal#xilinx_platform
booting the system without JTAG will be something you would need to work through based on the existing firmware design.
-Travis
Are you talking about this error?
How are you booting the system? Have you verified JTAG connectivity to the ARM and fabric?
-Travis
I couldn't verify the connection. I just wanted to test whether pluto is working or not. Is JTAG cable necessary?
How do you plan to program the device without JTAG?
-Travis
Hi , my name is Mac . I am currently a third-year student in Electronics and Telecommunication Engineering at KMUTT in Thailand
For now, i have a same problem with you to build the .xsa file from Vivado to Vitis / the point is there don't have the no-OS project of pluto-board and i am struggling to use Pluto as development board to do my Capstone project
If you have any information about this issue, Can you please provide it to me?
Best regards.
Mac
Hello,
We recommend opening a new thread, instead of replying to old ones, since there could be changes from one release to another and the issues/ solutions can be outdated.
Can you open a separate thread stating what Vivado version you are using, the HDL branch and any other helpful information so that we can properly help you?
Regards,
Stanca