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Xilinx Vivado/SDK HDL Wrapper

Category: Software
Product Number: AD9361
Software Version: Vivado 2022.2 / SDK 2014

By using github adalm-pluto hdl files, we built the fpga blocks of vivado. Now we want to wrap the design (Create HDL Wrapper) so that we can use the .xsa file in vitis or sdk. Even though we can export the hardware with bitstream, we can't add the file in SDK platform. How can we solve this issue?

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