I2C communication with ADALM2OOO Through Scopy

Hi:

The correct people to respond to this question are over in the Virtual Class room forum. Will try to move it over there.

ASuciu can you help this person please?

First of all, make sure that both I2C outputs are set to open-drain(the second picture suggests that they are not).

Also make sure that the pullup resistors are installed on the bus correctly - this is crucial for I2C to work.

The ADALM2000 is not a true I2C device. This means that it emulates an I2C by bitbanging rather than having dedicated hardware for this. This also means that the device cannot react in real-time to bus arbitration such as clock stretching, NACK, etc, and kinda assumes that everything will work - sometimes this happens, sometimes it doesn't. - more info here  Libm2k I2C Host Issues  

The part you are communicating to probably cannot keep up with the clocking provided by the ADALM2000, and may try stretching the clock. Since the ADALM2000 cannot respond to this, the whole communication can go sideways. In order to help it do this, set the samplerate of the I2C to a lower value and go upward from there. 1khz/10khz should be low enough. 

Thanks for the quick reply ASuciu ! amgadyousry please be kind enough to let ASuciu know if this answers your question.

thank you for your information. that was really useful, I have one more question. for the pattern generator if i am changing the frequency as marked in the first picture, what is the criteria of changing the sampling rate as shown in picture number 2. as I am bit confused between the sensor's scl clock frequency provided in the datasheet, i2c pattern's frequency and sampling rate in the logic analyzer. 

I am a little confused about your question.

According to the pictures:

The first piicture (logic analyzer) - has no frequency.

The second picture(pattern generator) has a frequency . The frequency represents the frequency of the I2C clocking. The pattern generator computes a sampling rate(144 samples at 481ksps sampling rate) based on this frequency to output the clocking(120Khz clock signal) - this happens behind the scenes and you shouldn't really care about this for this particular example. The 120kHz clock signal is provided to the sensor.

The logic analyzer has a sampling frequency that is independent from the pattern generator. This sampling frequency is used to acquire the signal and has no impact on the generated signal. It is a configuration parameter of acquiring back the signal in order to analyze it. In order to read back correctly, in theory the sampling frequency sohuld be at least 2x the signal under observation, however in practice you should go higher than this. 5MSPS >> 120kHz so you should be fine.

To reiterate, I don't think you'll get any results until you lower the i2c clocking frequency. Observing this signal correctly is just a question of having the sampling frequency a few times greater than this clocking frequency.