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IQ and DC offset correction in pluto hdl code

I saw in the hdl code that there is an IQ balance and DC offset correction. I know that there is already an IQ balance and DC offset correction inside the AD936x silicon, so I was wondering why there is another one in the hdl code. Robin Getz already told me, that the IQ balance correction in the hdl code is for syncing multiple pluto sdrs. Can somebody elaborate a bit, why an external IQ balance correction is needed when syncing multiple devices?

Besides that, I would like to know how I can control the hdl IQ balance and DC offset correction from the Linux driver?

Thanks!