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Q&A PLUTO sdr. Which part of the sdr system is implemented in FPGA?

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PLUTO sdr. Which part of the sdr system is implemented in FPGA?

greg@freshwaterbay.net on Jan 22, 2021

Is there any block diagram which shows what functionality in the signal processing chain is carried out in the FPGA? Thanks in advance.

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travisfcollins
Jan 22, 2021 +1 verified
Here is the closest diagram: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl

FMComms, ADRV936x, all share a similar structure if not identical.

By default, there is no DSP…

+1 travisfcollins

on Jan 22, 2021 5:40 PM 3 months ago
Here is the closest diagram: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl

FMComms, ADRV936x, all share a similar structure if not identical.

By default, there is no DSP applied to the datapaths for Pluto's RX and TX chains in the FPGA. However, you can enable extra decimate/interpolate by 8 in the data paths when using the DMAs. They are just inline with the DMAs and do not apply to the DDS path.

-Travis
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0 greg@freshwaterbay.net on Jan 22, 2021 6:57 PM 3 months ago in reply to travisfcollins

Thank you. I'll start by looking at the link.
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