Is there any block diagram which shows what functionality in the signal processing chain is carried out in the FPGA? Thanks in advance.
Here is the closest diagram: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl
FMComms, ADRV936x, all share a similar structure if not identical.
By default, there is no DSP applied to the datapaths for Pluto's RX and TX chains in the FPGA. However, you can enable extra decimate/interpolate by 8 in the data paths when using the DMAs. They are just inline with the DMAs and do not apply to the DDS path.