Hi,

This is my first time posting in the virtual classroom forum, but I thought my question would do better here as I am currently going through the "Software-Defined Radio for Engineers" book. (I am using an Fmcomms4+Zedboard instead of the Pluto SDR, but they should be very similar and my question is independent of this distinction).

So I am fairly comfortable working with using HDL and am attempting the offloading of some of the DSP functions that I have been using in GNU radio to the FPGA fabric of the Zynq. I know where to add them to the overall HDL reference design provided by Analog Devices. My confusion stems more from the digital BaseBand to RF side as I will explain below.

So I understand how the direct conversion transceiver works in general, but I am confused about how the actual 12 bit I and Q samples (which are in two’s complement representation) actually affect the phase of the overall RF signal! My current understanding:

Using the block diagram above for the Transmitter model. I feed 12 bit values from the AXI_ad9361 core to the RF daughter board (at the daughter boards clock (either 240Mhz or 120Mhz)) but the IP core only feeds one I sample or one Q sample at a time so the effective speed is half that for a pair (I_0,Q_0). The DAC (on the fmcomms-4 card) converts the 12 bit number(two’s complement) into a voltage with the extremum being at 0x7ff = 2047 decimal , and 0x800 = -2048 decimal. These represent the maximum relative voltage at the output of the DAC. This analog voltage value is then multiplied on either the carrier (TX LO ) for the Inphase component OR the Carrier with pi/2 phase increase for the Quadrature component. The I and Q components are then recombined at a final amplifier stage to produce the RF. Then my signal Mathematically looks like the following:

s(t)=I(t)*Cos(wrad/st)+Q(t)Cos(wrad/st+2)

Where I(t) and Q(t) are the output voltage values from the DAC.

Questions:

- Is my overall understanding and explanation above correct?

- If my final RF signal is indeed as I have described it above, then to alter the phase of the overall signal to achieve something like PSK one actually just controls the magnitude of the represented I and Q values in the overall signal. Is this statement correct (at least for direct conversion transceivers)?

Graph of the I(t)[Red] Q(t)[Blue] and there sum S(t) in Purple: - Are the digital FIR and interpolation filters in the RFIC (ad9363 for pluto or ad9364 for fmcomms4)?

My Goal in finally understanding all of this is to be able to intuitively offload functions to the FPGA and have "near" full control/understanding o the SDR!

This was a long post thanks for bearing with me and any help is appreciated !

Edit2: made image even larger

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**edited by:**RfStudent at 6:10 PM (GMT 0) on 19 Mar 2019]