Pluto HDL Interpolator/Decimator


We are exploring the possibility of removing the external decimator and interpolator from the pluto HDL reference design. 

We would like to explore being able to sample above 2MSPS as stated below from a previous post


The AD9363 has a minimum data rate of around 2 MSPS. The interpolator and decimator in the FPGA design are used to allow additional interpolation/decimation and a lower data rate.

If you do not intend to run with data rates below 2 MSPS you could potentially remove them, but be aware that the software expects them to be present so you might have to adjust the software as well.


From the HDL perspective, it looks like the interpolator and decimator, in addition to interpolation and decimation are taking two 16 bit streams of I and Q data and packing it into one 32 bit output which then goes to the ADC-DMA / DAC-DMA.

So from this standpoint, removing the interpolator and decimator would bring up another issue - still needing to pack the data appropriately. 

It looks like from this reference to receiving data, that the I and Q data are packed in an interleaving fashion, that is, I, Q, I, Q, I, Q....

	while (true) {
		void *p_dat, *p_end, *t_dat;
		ptrdiff_t p_inc;
		p_inc = iio_buffer_step(rxbuf);
		p_end = iio_buffer_end(rxbuf);
		for (p_dat = iio_buffer_first(rxbuf, rx0_i); p_dat < p_end; p_dat += p_inc, t_dat += p_inc) {
			const int16_t i = ((int16_t*)p_dat)[0]; // Real (I)
			const int16_t q = ((int16_t*)p_dat)[1]; // Imag (Q)
			/* Process here */

My first thought was to not remove the decimator/interpolator and to instead just decimate/interpolate x1.
In this way, I could still make use of the data packing portion of the HDL Blocks.

My only issue with that is that there may be some other HDL/IP that could do what I want, without using as much DSP.

Would something like an AXI4-Combiner be sufficient to do something like this?

Thank you for your time,
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