IIO: RX buffer is chopped and filled with zeros. RX/TX synchronization.

The main issue here is the sample rate you are selecting. You cannot set the sample rate below 2.08 MHz without loading an FIR. The radio is probably running at 30 or 60 MHz, which will cause underflows (starvation) and overflows (dropped data) on the TX and RX respectively. This is where the zeros come from.  We have a special functions for loading filters.  The easiest is here: https://github.com/analogdevicesinc/libad9361-iio/blob/c70ed5fe56624e420df87191d4288c3da82062c4/ad9361_baseband_auto_rate.c#L80

In general the latency between buffers will be fixed for a given simulation if you can keep up with the data streaming in. Otherwise you will have dropped some data on the floor and have no idea how much was lost. To help with things on the TX side I would recommend using cyclic buffers. That way you don't have to keep passing new data into the TX buffers.

Also know that you will have precision loss in your data since the part and HDL only use 12bits. Please this page about how data is cast inside the FPGA: https://wiki.analog.com/resources/fpga/docs/axi_ad9361#internal_interface_description

-Travis

Buffer push and fill are both blocking.

Either you create two processes. Or you pre-push some tx buffers, to fill the pipeline. Then create the rx buffer (since it's filling them once created) and then you enter your loop. 

-Michael

Hello Michael,

I knew that push and refill are both blocking. I assumed that when I call refill, it uses data it already gathered in some internal buffer, and just returns that buffer in a short time. I assumed that only if I called the refill again, that would block until I got enough samples. I see that I didn't understand the idea fully.

The information that the buffer is being filled right after it was created is an important one. It may be a reason of my phase shift jumping around - I create a RX buffer somewhere in the code without care.

But even if I use two processes, or pre-fill the TX pipeline, I don't see a good way to more or less synchronize TX and RX. If I understand correctly, whatever I do at the API level is several (not sure how many) buffers away from the AD936X digital interface. 

It would be nice to have IIO parameter to "hold" buffers on TX and "refilling" of RX buffers if set. That way I could prefill TX without pushing that out, then ask for RX buffer, and kick the parameter to start both RX and TX at the same time. I guess that would need to be done on hdl level?

I will start with pre-filling TX as you suggested. Any ideas how many buffers should I push on start?

Thank you a lot for your help,

Jerzy 

Hello Michael,

I knew that push and refill are both blocking. I assumed that when I call refill, it uses data it already gathered in some internal buffer, and just returns that buffer in a short time. I assumed that only if I called the refill again, that would block until I got enough samples. I see that I didn't understand the idea fully.

The information that the buffer is being filled right after it was created is an important one. It may be a reason of my phase shift jumping around - I create a RX buffer somewhere in the code without care.

But even if I use two processes, or pre-fill the TX pipeline, I don't see a good way to more or less synchronize TX and RX. If I understand correctly, whatever I do at the API level is several (not sure how many) buffers away from the AD936X digital interface. 

It would be nice to have IIO parameter to "hold" buffers on TX and "refilling" of RX buffers if set. That way I could prefill TX without pushing that out, then ask for RX buffer, and kick the parameter to start both RX and TX at the same time. I guess that would need to be done on hdl level?

I will start with pre-filling TX as you suggested. Any ideas how many buffers should I push on start?

Thank you a lot for your help,

Jerzy 

Its not really how many buffers, its more about the data. The max buffer is 2^24 by default, which should keep the DMA busy for awhile.

-Travis