I have a xilinx usb jtag programmer version 2 like this:
HW-USB-II-G XILINX, Cable, Platform Cable USB II, Configuración y Programación en Circuito de Dispositivos Xilinx | Farn…
And I would like to know is there any special advice to connect it directly to adalm-pluto jtag.
the xilinx programmer has 7 pins menawhile the pluto connector has a 8 pins connector for jtag a serial.
I can seen there is 4 signals identical between xilinx jtag and pluto jtag (TMS,TCK,TDI and TDO) and of course the ground.
but I don't know what to do with the others (Vref and Halt) and also if there is another signals in adalm pluto to take in account.
I'll be gratefull if you could provide some gidance in steps to do to be able to program the adalm pluto with an external programmer.
P.D. also the rev. C would be great if you could insert a jtag connector without have to solder anything.
Please see here: https://wiki.analog.com/university/tools/jtaguart
Why not look at the schematics?
Yes - Pin 5 of the Pluto header will connect to MIO5 aka. BOOT_MODE.
This either selects QUAD-SPI or JTAG Boot Mode.
But be aware while this pin is grounded - you can't access the QUAD-SPI.
HALT is purely optional and a output of the JTAG probe.
Just leave it floating.
I knew about this programmer but I was'nt sure about some signals.
I assume then I have to left open the halt signal from jtag xilinx programmer and ground the 5 pin of the FTSH connector for jtag boot or I have to connect both?.
regarding the vref in xilinx Jtag I have to connect it to pin 10 of I can left it open?.
I have seen the schematis and is not clear the meaning of some signals.
for example in the jtag connector of adalm jtag-uart the pins 12 and 14 are set as spare pins menawhile in xilinx-jtag programmer the 12 pin is for halt signal.
OK, just for clarify I have to left open the halt signal from jtag xilinx programmer and ground the 5 pin of the FTSH connector for jtag boot. the tdi and TDO should be crossed and the TMS and TCK directly connected.