ADALM2000 - Debugging SPI

The objective of this tutorial is to use the Logic Analyzer instrument provided by the ADALM2000 (M2K) board and the Scopy software toolset to visualize SPI (Serial Peripheral Interface) transactions between two devices.

The Total Dissolved Solids Measurements Demo (TDS) project will be used as an example. The project uses the EVAL-CN0411-ARDZ shield mounted to the EVAL-ADICUP360 microcontroller board. The shield includes two SPI devices: a AD5683R, 16-bit, voltage-output DAC, and a AD7124-8, low noise, low power, 24-bit Sigma-Delta ADC.

The TDS project includes a function to set the DAC voltage and read it back via the ADC, providing a complete example of a SPI transaction for analysis. (for more details on how setup and use the software, please refer to the TDS Demo link above).


Serial peripheral interface (SPI) is one of the most widely used interfaces between microcontrollers and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAM, and others. It is a synchronous, serial, full-duplex, master-slave-based interface used for short distance communication, usually on the same PC board. Data transfer is synchronized by a clock, where data can be read on the rising or falling clock edge, depending on the mode. Separate signals are used for data from the master to the slave and vice-versa, such that both master and slave can transmit data at the same time.

Figure 1. SPI master-slave configuration

The SPI bus includes four logic signals:

  • CS: Chip Select or Slave Select (often active low, output from master)
  • SCLK: Serial Clock (output from master)
  • MOSI: Master Output Slave Input, or Master Out Slave In (data output from master)
  • MISO: Master Input Slave Output, or Master In Slave Out (data output from slave)

A typical full-duplex SPI interface uses all four of these signals, and is referred to as a “4-wire” interface. 3-wire interfaces may be employed where only unidirectional communication is required. For example, a single-channel ADC that does not require any configuration may only have CS, SCLK, and MISO signals. Similarly, a single-channel DAC may only have CS, SCLK, and MOSI signals. This tutorial will focus on the 4-wire SPI interface.

The Chip Select (CS) signal from the master is used to select a single slave and enable its SPI interface. Usually it is an active low signal; a high level will disable the slave device such that it ignores any activity on the SPI bus and tri-states its MISO output. When multiple slaves are used, an individual chip select signal is required for each slave device. Only the selected slave device (whose CS signal is asserted) is allowed to drive MISO. (The master drives SCK and MOSI signals continuously, idling high or low between transactions depending on the SPI mode.)

The device that generates the clock signal (SCLK) is called the master. Data transmitted between the master and the slave is synchronized to the clock generated by the master. SPI interfaces can have only one master and can have one or multiple slaves.

MOSI and MISO are the data lines. MOSI transmits data from the master to the slave and MISO transmits data from the slave to the master. (As noted in the CS signal description, only one slave device drives MISO at a time.)

To begin SPI communication, the master must select a slave by asserting its CS signal. During SPI communication, the data is simultaneously transmitted (shifted out serially onto the MOSI bus) and received (the data on the MISO bus is sampled or read in). The active serial clock edge synchronizes the shifting and sampling of the data.

The SPI interface may use one of four modes defined by two parameters, CPOL and CPHA, which specify whether the rising or falling edge of the clock is used to sample and/or shift the data, and whether the clock idles high or low between transactions. It is essential that the master and slave are configured to the same SPI mode - often the slave device's mode is fixed, while the master's can be configured either at run-time (as is often the case for microcontrollers and microprocessors) or at compile-time (as is the case with some FPGA SPI IP cores).

Figure 2. SPI Modes

CPOL stands for Clock POLarity and designates the default value (high/low) of the SCK signal when the bus is idle. CPHA stands for Clock PHAse and determines which edge of the clock data is sampled (rising edge/falling edge). The data sheet for the slave device will specify these parameters so that the master can be configured accordingly.

An example of SPI transfers for the two CPOL configurations is presented in Figure 3. 8 data bits are sent, starting with MSB.

Figure 3. SPI Transfer Example

Hardware Configuration

Figure 4. shows the hardware connection between M2K board and EVAL-ADICUP360 + EVAL-CN0411-ARDZ shield.

Figure 4. SPI Debug Hardware Setup

The SPI pins for the CN0411 shield are available for monitoring at port DIGI1. Since we have 2 slaves connected to the master (ADC and DAC), there are 2 pins corresponding to the Chip Select of each slave.

EVAL-CN011-ARDZ SPI pin configuration: Port DIGI1:

  • Pin2 - CS ADC
  • Pin3 - CS DAC
  • Pin4 - MOSI
  • Pin5 - MISO
  • Pin6 - SCLK

Port POWER1:

  • Pin6 - DGND

M2K SPI pin configuration:

  • DIO0 - SCLK
  • DIO1 - MISO
  • DIO2 - MOSI
  • DIO3 - CS
  • GND - DGND

Connect the M2K pins to the CN0411 as follows:

  • Pin2 (ADC) or Pin3 (DAC) - DIO3
  • Pin4 - DIO2
  • Pin5 - DIO1
  • Pin6 - SCLK

Scopy Logic Analyzer Configuration

Several SPI configuration parameters need to be determined in order to properly configure Scopy. For the CN0411 project, they are as follows:

  • SPI Clock rate - 1MHz
  • CPOL - High (1) for ADC and DAC
  • CPHA - High (1) for ADC and Low (0) for DAC
  • Bits per Transfer (Word size): 8
  • CS Polarity - enable transfer when line is active low
  • Most Significant Bit (MSB) is transmitted first

An overview of the user interface is shown in Figure 5.

Figure 5. Scopy SPI Debug Setup

Open the Logic Analyzer instrument, select DIO0-DIO3 lines and press the “Group with selected” button.

Figure 6. Logic Analyzer group channels

Select the channel group formed and apply the SPI decoder. While the group is selected, open settings menu by pressing the  button on the top right side of the user interface. A settings panel will appear for the SPI decoder, allowing the signal-channel configuration and parameters setup. Apply the parameters listed above to the group, noting that ADC and DAC have a different Clock Phase setting.

Figure 7. Group Settings

The Logic Analyzer must be set up to “catch” the SPI transfer on the Logic Analyzer plot. Therefore we need to configure a trigger. Since the SPI transfer starts when the Chip Select signal is asserted low, the falling edge of the CS channel can be used as the trigger.

Figure 8. Trigger Settings

SPI Transmit

This example verifies that for a given software command, the correct configuration bits and output code are sent to the DAC. Make sure that the correct DAC CS pin is connected to the M2K digital pin (see Hardware Configuration step).

To set the DAC output to 1.0V, the value that needs to be written can be computed using the DAC voltage-to-value formula:

Set the Time Base of the Logic Analyzer instrument to 10us and the Trigger Position at 35us and run a Single sweep.

Figure 9. General Settings

The Logic Analyzer will wait for the falling edge of the CS signal to be triggered.

Run the “setdac 1.0” command. This will initiate the SPI transmission.

The result is presented in Figure 10.

Figure10. SPI Write sequence

Analyzing the plot, 3 bytes (24 bits) are sent on the MOSI line, starting with MSB. The first four bits correspond to the command bits, 0x3, which is the “Write DAC and input register” command. This is followed by 16 bits representing the DAC output code computed previously (0x6666). The final four bits are “don't care”, and are set to zero in the software (although they do not have to be zero.)

SPI Receive

The ADC output code will now be analyzed to confirm that it corresponds to 1.0V. (The voltage at the DAC output can also be double-checked with a voltmeter if desired.)

First, connect the M2K DIO3 pin to the ADC CS pin (DIGI1 Pin 2). Since the SPI configuration slightly differs from the one of the DAC (See SPI parameters list), modify the group settings menu, setting the Clock Phase (CPHA) to 1.

Run a Single Sweep on the Logic Analyzer instrument again and run the “readdac” command. This will read the ADC channel corresponding to the DAC output.

The result is shown in Figure 11.

Figure 11. SPI Read sequence

The data on the MOSI line corresponds to the ADC's register address (0x42) followed by three dummy bytes (0x00) while the register value is being received.

While the dummy bytes are being sent, the ADC simultaneously sends the 24-bit value stored in the requested register on the MISO line (0x665DBF).

The ADC code can then be converted to voltage using the following formula:

As expected, the DAC voltage is very close to the voltage that the DAC was set to previously.

Therefore, we can conclude that SPI communication, both writing and reading, worked properly.


In addition to SPI, the application includes a set of decoders covering a large number of communication protocols such as I2C, I2S, UART, JTAG, and others, making ADALM2000 a powerful tool for analyzing and debugging digital signals.

  • Hello,
    I have a question about the polarity and the clock phase please,
    In the figure Figure 2. SPI Modes, this picture demonstrate the polarity and phase, does this logic is the same for the ADALM2000?
    polarity and clock phase are different, it depend the supplier of the microcontroller.

    •  Analog Employees 
    11 months ago

    Hello Jon, you can export data from logic analyzer into .csv files. For larger data logging, please use the streaming mode. After you acquired enough data for your analysis, just press the export button.

    •  Analog Employees 
    11 months ago in reply to tai

    Hello Tai, sorry for the late response. There is a spinbox in the Logic Analyzer instrument where you can set the sampling frequency.

  • Where in the screenshot is sampling frequency set for the logic analyzer?