tddn off_raw parameter

Hello,

The on_raw and off_raw attributes control the time from the beggining of the initial pulse trigger until the start and end respectively of the first pulse on the channel. This way, based on the configuration of frame lentgh on_raw and off_raw, one can control the duty_cycle of the pulse on the tdd channel. The attributes on_raw and off_raw specify raw values, the conversion in ms is available via the off_ms and on_ms attributes, available in the tddn class: https://github.com/analogdevicesinc/pyadi-iio/blob/main/adi/tddn.py#L171. Therefore, off_raw = 10 would translate to about 0.000040 from the initial trigger to the end of your channel's pulse, and then it stays low until the end of the frame length. If for a specific use case you need your pulse to stay in the reerse state for a certain period of time, you would need to set off_raw accordingly or simply set "off_ms" for that period.

Channel 0 is most likely the enable channel, that channel is probably not tied to anything else but it is necessary to be enabled in order to enable the rest of the tdd channels, that's why no particular configuration is necessary for it.

Finally, polarity refers to the polarity of the tdd channel, if it's regular polarity (from 0 to 1)  or inverse polarity (from 1 to 0).

I hope this clarifies the attributes and their purpose a bit. Please let me know if you have any additional questions. I attach below a diagram that shows the timing.

Thank you for the explanation and the diagram. That makes things much clearer, but I still have some questions.

• off_raw = 10 would translate to about 0.000040
  
  How is every clock cycle 4 microseconds? Isn't the Pluto oscillator 40 Mhz which is what is used by the Zynq?
  
  
• polarity refers to the polarity of the tdd channel
  
  I don't understand what "polarity of the channel" means in general. Can you provide an explanation or link to some relevant educational resource?

Finally, can you help me clarify why the DMA channels are high for only 10 clock cycles? I don't have experience with digital systems outside a single university course. I had a look at the HDL project in Vivado, and the RX DMA TDD channel connects to the "fifo_wr_sync" input of the ADC's DMA controller. The triangle on the input means it only reads a rising edge, correct? So the TDD DMA channels only need a short pulse to synchronize?

This "fifo_wr_sync" is not present in the AXI DMAC core documentation, some more explanation on the synchronization mechanism would be nice.

The TX's channel I don't understand how it works, or why it is HIGH for 10 clock cycles. It connects to an OR gate together with a "rst" signal from the ad9361 core, whose result goes to the "reset" input of a "upack" core. The reset seems to be logical and not edge based, so it sound like the length of time the TX channel is held at HIGH seems important. Can you provide some explanation on how the TX synchronization works?

Hi JHPereira!
Regarding the HDL, could you please provide more details about your design? Are you using the Pluto project from a release or did you build it from the latest HDL main branch? Did you modify the design, have you implemented custom logic?

Regards,
Cristian

Hello. I'm using Pluto firmware v0.39 with no modification. The image I showed was built from the Pluto project in the Analog Devices HDL github repo, which I assume is the same, and used it just for analysis.

Hello. I'm using Pluto firmware v0.39 with no modification. The image I showed was built from the Pluto project in the Analog Devices HDL github repo, which I assume is the same, and used it just for analysis.