Hello,
I am working on a bare-metal, no-OS bring-up of the AD9363A on an ADALM-Pluto-derived hardware platform.
The RFPLL fails to complete VCO calibration, and I consistently receive:
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VCO_LOCK_REG (0x247) = 0x80 (CP_OVRG_HIGH)
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Calibration return code = –116
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PLL does not lock on either TX or RX paths.
My reference clock is 40 MHz, and the computed VCO frequency (from ad9361_calc_rfpll_int_divider()) is typically ~9.44–9.60 GHz.
The stock AD9361 SynthLUT from no-OS is being used, but the selected VCO entries around 9445–9631 MHz consistently fail to lock on my AD9363 hardware.
I understand that AD9363 devices rely on a different set of VCO calibration parameters, and that these may be factory-trimmed and not present in the AD9361 public LUT. Since these values are critical (varactor offset, VCO bias, charge pump current, calibration offsets, etc.), I would like to confirm the correct values for the AD9363.
Could you please provide one of the following?
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The official AD9363 LUT (VCO_MHz, Varactor, CP current, offsets, etc.) corresponding to a 40 MHz reference clock,
OR -
The factory-programmed VCO calibration parameters used on ADALM-Pluto AD9363 parts (if generic),
OR -
The recommended procedure for manually adjusting CP current / varactor / VCO calibration offsets for AD9363 at ~9.4–9.6 GHz VCO.
Additional Technical Information
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Using no-OS driver, bare-metal (no Linux).
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Hardware is verified; SPI, reference clock, power rails, and RF front-end biasing are correct.
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Register dump of failure shows:
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REG_RX_CP_OVERRANGE_VCO_LOCK= 0x80 -
REG_RX_VCO_CAL_STATUS= 0x84
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The PLL never achieves lock during calibration.
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Adjusting CP current, varactor reference, or selecting different LUT entries only shifts the failure.
Since the AD9363 uses internal factory-trimmed VCO tables that differ from AD9361, having the correct calibration parameters is essential for proper bring-up.
Any guidance, documentation, or official parameter tables would be greatly appreciated.
Thank you,
Prasanna
