Changing the ADALM2000 reference clock from the standard 100MHz

Question

The standard ADALM2000 uses a pll chip ( ADF4360-9) to generate 100MHz clock for the ADC. I'd like to set the pll chip to output 80MHz ... which should be an easy! 
 However, the scopy client app seems to only set a specific decades of sampling rates i.e. 100, 10, 1 MSPS 
 From a terminal window into ADALM2000, I can observe the pll's sysfs attribute: 
 # ./cat_iio_device_pll_attributes

Running script cat_iio_device_pll_attributes
name
pll

out_altvoltage0_frequency
100000000

out_altvoltage0_mute_till_lock_detect
1

out_altvoltage0_muxout_mode
lock-detect

out_altvoltage0_pfd_frequency
5000000

out_altvoltage0_power_down
normal

out_altvoltage0_power_level
5000-uA

out_altvoltage0_refin_frequency
20000000

out_altvoltage_muxout_mode_available
three-state lock-detect ndiv dvdd rdiv od-ld sdo gnd

out_altvoltage_power_down_available
normal soft-async ce soft-sync regulator

out_altvoltage_power_level_available
3500-uA 5000-uA 7500-uA 11000-uA

This shows the kernel driver for pll reporting a 100MHz output. However if if try to write into anything other than 10000000 into out_altvoltage0_frequency scopy spectrum analyzer freezes ... but unfreezes if 100000000 is written. 
 # echo 100000000 > /sys/bus/iio/devices/iio:device3/out_altvoltage0_frequency
# echo 80000000 > /sys/bus/iio/devices/iio:device3/out_altvoltage0_frequency
# echo 100000000 > /sys/bus/iio/devices/iio:device3/out_altvoltage0_frequency
 
 What can I do to see a spectrum from the ADC for sample rates other than the standard ones ? 
 DrFlute1

andrei_g · Accepted Answer

Hi, I have to start with noting that we cannot support this feature for you, and only can give you pointers. The adf clock drives ad9963. M2k probably freezes because the PLLs inside AD9963 gets out of sync. The AD9963 drive the FPGA fabric through interface clocks (adc/dac). So, you should consider the rest of the data path, I belove this cannot be done through simple IIO reads and writes for frequency attributes. I would start from the devicetree: adf settings: linux/arch/arm/boot/dts/xilinx/zynq-m2k-reva.dts at main &middot; analogdevicesinc/linux converter (ad9963) clock: linux/arch/arm/boot/dts/xilinx/zynq-m2k-reva.dts at main &middot; analogdevicesinc/linux Another suggestions would be to look at adc_decimate AXI_ADC_DECIMATE [Analog Devices Wiki] If you remove the fir filter you could get a 5/50/500... decimation ratio. 96 MHz is a 19.2 MHz x 5. but that implies changing the HDL and Linux driver, if you succeed you will have to adjust for amplitude compensations. 
 DrFlute1 said: 3) Create my own iio client app to exercise ADLAM2000 instead of scopy. 
 There are python bindings for libm2k, you don't need an app, a script might be enough, python can plot and accept gui inputs. Andrei)

DrFlute1 · Answer

Hi andrei_g 
 Thanks for the excellent advice ... your pointers are just what I needed. 
 Replacing the reference design fir filter with a downsampling filter is my next task. I actually need an output sample rate out of 4.8MSPS so downsampling by 20 from 96MSPS will do the job (perhaps a CIC to downsample by 10 followed by a compensation FIR do the final downsample by 2). 
 Also, I've succeeded in setting the PLL chip to produce a 96MHz clock reference for the ADC ... and verified this using a lab scope. Other values seem to freeze the clock ... which, in turn, causes the scopy spectrum analyzer to freeze. 
 // pll driver reports 100MHz AND pll chip outputs 100MMz
# iio_attr --channel-attr pll altvoltage0 frequency
100000000

// Values of 50 and 60 MHz are rejected by the pll driver AND pll chip continuea outputting 100MMz
# iio_attr --channel-attr pll altvoltage0 frequency 50000000
error Invalid argument (22) while writing 'frequency' with '50000000'

# iio_attr --channel-attr pll altvoltage0 frequency 60000000
error Invalid argument (22) while writing 'frequency' with '60000000'

// Values of 70 and 80 MHz are accepted by the pll driver BUT pll chip outputs no clock 
# iio_attr --channel-attr pll altvoltage0 frequency 70000000
70000000

# iio_attr --channel-attr pll altvoltage0 frequency 80000000
80000000

// Value of 96 MHz is accepted by the pll driver AND pll chip produces clock at 96MHz
# iio_attr --channel-attr pll altvoltage0 frequency 96000000
96000000 
 I suspect there are other pll chip setting that must be made for frequencies such as 80MHz ... I'll have to read the data sheet. 
 Finally, using Python to call libm2k will surely save me time. 
 Kind regards 
 DrFlute1

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Changing the ADALM2000 reference clock from the standard 100MHz

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