Changing the ADALM2000 reference clock from the standard 100MHz

... to be thorough, I've tried setting the pll output using iio_attr ... same result: scopy freezes for 80MHz but unfreezes when I restore 100MHz

# iio_attr --channel-attr pll altvoltage0 frequency
100000000
# iio_attr --channel-attr pll altvoltage0 frequency 80000000
80000000
# iio_attr --channel-attr pll altvoltage0 frequency
80000000
# iio_attr --channel-attr pll altvoltage0 frequency 100000000
100000000

Hello DrFlute1 ,

At first glance, please take a look at this thread regarding your issue with changing the ADALM2000 reference clock: ADALM2000 sampling - Q&A - Virtual Classroom for ADI University Program - EngineerZone .

The thread discusses related sampling rate limitations and might provide useful information.

Best regards,

Maria

Hello mandrica ,

Thanks for your reply ... it's good to have your help.

I had a look at the link you sent me ... and it seems that the user is doing sample rate conversion before the DAC so that it can use the same rate as the ADC i.e. 100 KSPS. In my case, I need to set the ADC sample rate to a very specific 19.2 MSPS (appropriate to the symbol rate of the incoming signal) ... yes, I did say 80MHz in my original post but I was trying simplify the question!

I should be able achieve 19.2 MSPS by tweaking the pll chip  (ADF4360-9) and maybe changing the reference osc. As mentioned before, I've tried telling the pll linux driver (adf4360,c) to set for 80MHz ... but this is where the scopy stops receiving samples. So now I'm thinking ...

1) See the pll output on a scope. Is it producing the frequency I've told the pll driver to set?

2) Change the device tree binary so that the ADALM2000 knows the new sample rate on bootup.

3) Create my own iio client app to exercise ADLAM2000 instead of scopy.

If I do find a solution, I'll be sure to post it for the benefit of others.

Kind regards

DrFlute1

Hi,

I have to start with noting that we cannot support this feature for you, and only can give you pointers.

The adf clock drives ad9963. M2k probably freezes because the PLLs inside AD9963 gets out of sync. The AD9963 drive the FPGA fabric through interface clocks (adc/dac).
So, you should consider the rest of the data path, I belove this cannot be done through simple IIO reads and writes for frequency attributes.
I would start from the devicetree:
adf settings:  linux/arch/arm/boot/dts/xilinx/zynq-m2k-reva.dts at main · analogdevicesinc/linux
converter (ad9963) clock: linux/arch/arm/boot/dts/xilinx/zynq-m2k-reva.dts at main · analogdevicesinc/linux

Another suggestions would be to look at adc_decimate AXI_ADC_DECIMATE [Analog Devices Wiki]
If you remove the fir filter you could get a 5/50/500... decimation ratio. 96 MHz is a 19.2 MHz x 5. but that implies changing the HDL and Linux driver, if you succeed you will have to adjust for amplitude compensations.

DrFlute1 said:

3) Create my own iio client app to exercise ADLAM2000 instead of scopy.

There are python bindings for libm2k, you don't need an app, a script might be enough, python can plot and accept gui inputs.

Andrei

Hi andrei_g 

Thanks for the excellent advice ... your pointers are just what I needed.

Replacing the reference design fir filter with a downsampling filter is my next task. I actually need an output sample rate out of 4.8MSPS so downsampling by 20 from 96MSPS will do the job (perhaps a CIC to downsample by 10 followed by a compensation FIR do the final downsample by 2).

Also, I've succeeded in setting the PLL chip to produce a 96MHz clock reference for the ADC ... and verified this using a lab scope. Other values seem to freeze the clock ... which, in turn, causes the scopy spectrum analyzer to freeze.

// pll driver reports 100MHz AND pll chip outputs 100MMz
# iio_attr --channel-attr pll altvoltage0 frequency
100000000

// Values of 50 and 60 MHz are rejected by the pll driver AND pll chip continuea outputting 100MMz
# iio_attr --channel-attr pll altvoltage0 frequency 50000000
error Invalid argument (22) while writing 'frequency' with '50000000'

# iio_attr --channel-attr pll altvoltage0 frequency 60000000
error Invalid argument (22) while writing 'frequency' with '60000000'

// Values of 70 and 80 MHz are accepted by the pll driver BUT pll chip outputs no clock 
# iio_attr --channel-attr pll altvoltage0 frequency 70000000
70000000

# iio_attr --channel-attr pll altvoltage0 frequency 80000000
80000000

// Value of 96 MHz is accepted by the pll driver AND pll chip produces clock at 96MHz
# iio_attr --channel-attr pll altvoltage0 frequency 96000000
96000000

I suspect there are other pll chip setting that must be made for frequencies such as 80MHz ... I'll have to read the data sheet.

Finally, using Python to call libm2k will surely save me time.

Kind regards

DrFlute1

Hi andrei_g 

Thanks for the excellent advice ... your pointers are just what I needed.

Replacing the reference design fir filter with a downsampling filter is my next task. I actually need an output sample rate out of 4.8MSPS so downsampling by 20 from 96MSPS will do the job (perhaps a CIC to downsample by 10 followed by a compensation FIR do the final downsample by 2).

Also, I've succeeded in setting the PLL chip to produce a 96MHz clock reference for the ADC ... and verified this using a lab scope. Other values seem to freeze the clock ... which, in turn, causes the scopy spectrum analyzer to freeze.

// pll driver reports 100MHz AND pll chip outputs 100MMz
# iio_attr --channel-attr pll altvoltage0 frequency
100000000

// Values of 50 and 60 MHz are rejected by the pll driver AND pll chip continuea outputting 100MMz
# iio_attr --channel-attr pll altvoltage0 frequency 50000000
error Invalid argument (22) while writing 'frequency' with '50000000'

# iio_attr --channel-attr pll altvoltage0 frequency 60000000
error Invalid argument (22) while writing 'frequency' with '60000000'

// Values of 70 and 80 MHz are accepted by the pll driver BUT pll chip outputs no clock 
# iio_attr --channel-attr pll altvoltage0 frequency 70000000
70000000

# iio_attr --channel-attr pll altvoltage0 frequency 80000000
80000000

// Value of 96 MHz is accepted by the pll driver AND pll chip produces clock at 96MHz
# iio_attr --channel-attr pll altvoltage0 frequency 96000000
96000000

I suspect there are other pll chip setting that must be made for frequencies such as 80MHz ... I'll have to read the data sheet.

Finally, using Python to call libm2k will surely save me time.

Kind regards

DrFlute1