ADQUADMXFE1EBZ MultiChip Sync

Hi Lucian,

Thank you for reaching out.

A workflow that has achieved MCS on the Quad-MxFE Platform can be viewed in Figure 2 at the link below.

https://www.analog.com/en/technical-articles/power-up-phase-determinism-using-multichip-synchronization.html

Additional details regarding the MCS process can be viewed at the link below:

https://wiki.analog.com/resources/eval/user-guides/quadmxfe/multichipsynchronization

It sounds as though you are already familiar with some of the example MATLAB scripts for the platform given your comment above, but details on the example MATLAB script to achieve MCS is shown at the link below and is available in the QuadMxFE_MCS.m script available within the High-Speed Converter Toolbox:

https://wiki.analog.com/resources/eval/user-guides/quadmxfe/quickbringup#quadmxfe_mcsm

For the demonstrations we leverage the ADI JESD204C IP. Can you please confirm that you can achieve MCS on the platform using these existing example scripts? Will you plan to leverage the ADF4371 PLL as the clock source for the AD9081?

https://wiki.analog.com/resources/eval/user-guides/quadmxfe/quick-start#software

The example HDL Reference Design is shown in the link below:

https://wiki.analog.com/resources/eval/user-guides/ad_quadmxfe1_ebz/ad_quadmxfe1_ebz_hdl

All the Best,

Mike

Hi Mike, 

Maybe i was not too exaustive in my explanation.We are very familiar with the articles on the Wiki and also the reference designs that you send me, since we use that as example. However we actually working on a custom architecture different from your example as we are creating a custom board for a client.

The syncronization and all your examples are ok with the VCU118 and Quad MxFE RevC however that is not what we need. 

LGChiriac said:

I'm actually working on the QuadMxFE Platform Rev.B with a custom FPGA design composed by a Petalinux Distribution and custom Software and custom firmware using the Xilinx JESD204 IP Core.

The FPGA is different from VCU118 and all the architecture, FW, Software, HW is custom. We only use the Quad MxFE Rev.B as evaluation board. 

My doubt was about specific signals issues and algorithm "stages", more specific and detailed of your Wiki articles. The general description of the algorithm is ok and i have no issues with that. 

I've asking for a design workflow, is ok that is described in Figure 2:

wmjones2 said:

A workflow that has achieved MCS on the Quad-MxFE Platform can be viewed in Figure 2 at the link below.

https://www.analog.com/en/technical-articles/power-up-phase-determinism-using-multichip-synchronization.html

But we are not able to understand which API needs to be used in order to execute every stage. And also there are not specified which conditions need to be guaranteed or controlled at the end of at the beginning of the stages. 

For example, as described in Figure 2 of your article, the MCS routine is executed until there is no Phase Slip between the SYSREF and LEMC.

LGChiriac said:

I suppose that routine is enabled by the Matlab Code: "tx.setDeviceAttributeRAW('multichip_sync', '10', tx.iioDev3); %Issue MCS" and is executed until the phase bewteen SYSREF and LEMC is null.

Strobbing and reading the register 0x00B5 and 0x00B6 (i use also the API to read that) for each update and reading (successive) the SYSREF-LEMC phase is variable. Is that a normal? I think NO, but i not have any article or wiki document that explain that. On the UG is not specified how this phase is. I'm expecting that phase value remains constant when i reading it maybe 2-3 times. Maximum i'm expecting a little variation in DAC clock cycles but i reading variation like 1000,2000 DAC clocks for each time i strobe that registers. 

When using One SHOT SYSREF, in the registers 0x0FB7, 0x0FB8  the value that i'm reading is related to the first time when SYSREF was sampled or is updated every time? If this registers are updated every time, when the sysref is off, what i read in those registers? 

Can you provide a response at this questions? i'm not able to find any low level descripted workflow to use as reference. The Wiki articles are ok but the discription is high level and too generic. 

Thank you.

-Lucian.

Hi Mike, 

Maybe i was not too exaustive in my explanation.We are very familiar with the articles on the Wiki and also the reference designs that you send me, since we use that as example. However we actually working on a custom architecture different from your example as we are creating a custom board for a client.

The syncronization and all your examples are ok with the VCU118 and Quad MxFE RevC however that is not what we need. 

LGChiriac said:

I'm actually working on the QuadMxFE Platform Rev.B with a custom FPGA design composed by a Petalinux Distribution and custom Software and custom firmware using the Xilinx JESD204 IP Core.

The FPGA is different from VCU118 and all the architecture, FW, Software, HW is custom. We only use the Quad MxFE Rev.B as evaluation board. 

My doubt was about specific signals issues and algorithm "stages", more specific and detailed of your Wiki articles. The general description of the algorithm is ok and i have no issues with that. 

I've asking for a design workflow, is ok that is described in Figure 2:

wmjones2 said:

A workflow that has achieved MCS on the Quad-MxFE Platform can be viewed in Figure 2 at the link below.

https://www.analog.com/en/technical-articles/power-up-phase-determinism-using-multichip-synchronization.html

But we are not able to understand which API needs to be used in order to execute every stage. And also there are not specified which conditions need to be guaranteed or controlled at the end of at the beginning of the stages. 

For example, as described in Figure 2 of your article, the MCS routine is executed until there is no Phase Slip between the SYSREF and LEMC.

LGChiriac said:

I suppose that routine is enabled by the Matlab Code: "tx.setDeviceAttributeRAW('multichip_sync', '10', tx.iioDev3); %Issue MCS" and is executed until the phase bewteen SYSREF and LEMC is null.

Strobbing and reading the register 0x00B5 and 0x00B6 (i use also the API to read that) for each update and reading (successive) the SYSREF-LEMC phase is variable. Is that a normal? I think NO, but i not have any article or wiki document that explain that. On the UG is not specified how this phase is. I'm expecting that phase value remains constant when i reading it maybe 2-3 times. Maximum i'm expecting a little variation in DAC clock cycles but i reading variation like 1000,2000 DAC clocks for each time i strobe that registers. 

When using One SHOT SYSREF, in the registers 0x0FB7, 0x0FB8  the value that i'm reading is related to the first time when SYSREF was sampled or is updated every time? If this registers are updated every time, when the sysref is off, what i read in those registers? 

Can you provide a response at this questions? i'm not able to find any low level descripted workflow to use as reference. The Wiki articles are ok but the discription is high level and too generic. 

Thank you.

-Lucian.