QUAD MxFE Multi-Chip Sync (MCS) TXMODE9/RXMODE10(M8,L4)

Hi all,

As my previous questions i'm working on yours evaluation board Quad MxFE. In order to reach my customer specifications i need to use a JESD configuration that is JESD204B, TX mode 9, RX mode 10 (M8, L4) with a SampleRate=125Msps, FDAC=4GHz and FADC=2GHz. The build works but i need to compute the MCS in order to achieve all channel syncronization. 

The first issue that i encountered was about power level of the signal in this new custom mode. In this configuration, the power of received signal is about -32dBm, i was able to raise that level to -26dBm considering settings suggested in this thread:  RE: Quad MxFe arbitrary JESD204B Lane Rates .

I figure out how to adapt the MCS Matlab script in order to achieve the chip syncronization. Since the default script suppose that all the FDDCs are enabled, i added the settings about the TX struct in order to reduce the number of enabled channels

%% Setup Tx Information
        tx = adi.QuadMxFE.Tx;
        tx.UpdateDACFullScaleCurrent = true;
        tx.DACFullScaleCurrentuA = 40000;

        tx.CalibrationBoardAttached = useCalibrationBoard; %0: Not Using Calibration Board, 1: Using Calibration Board
        tx.uri = uri;

        tx.num_coarse_attr_channels = 4; %Number of Coarse DUCs Used Per MxFE
        tx.num_fine_attr_channels = 4; %Number of Fine DUCs Used Per MxFE
        tx.num_data_channels = 4*tx.num_fine_attr_channels; %Total Number of Fine DUCs Used In System
        tx.num_dds_channels = tx.num_data_channels*4; %Total Number of DDSs Used In System (Not Used For 'DMA' Mode)
        
        tx.ChannelNCOGainScalesChipA  = zeros(1,tx.num_fine_attr_channels); %MxFE0 Digital Gain Code
        tx.ChannelNCOGainScalesChipB  = zeros(1,tx.num_fine_attr_channels); %MxFE1 Digital Gain Code
        tx.ChannelNCOGainScalesChipC  = zeros(1,tx.num_fine_attr_channels); %MxFE2 Digital Gain Code
        tx.ChannelNCOGainScalesChipD  = zeros(1,tx.num_fine_attr_channels); %MxFE3 Digital Gain Code
        tx.MainNCOFrequenciesChipA = zeros(1,tx.num_coarse_attr_channels); %MxFE0 Coarse DUC NCO Frequencies [Hz]
        tx.MainNCOFrequenciesChipB = zeros(1,tx.num_coarse_attr_channels); %MxFE1 Coarse DUC NCO Frequencies [Hz]
        tx.MainNCOFrequenciesChipC = zeros(1,tx.num_coarse_attr_channels); %MxFE2 Coarse DUC NCO Frequencies [Hz]
        tx.MainNCOFrequenciesChipD = zeros(1,tx.num_coarse_attr_channels); %MxFE3 Coarse DUC NCO Frequencies [Hz]
        tx.ChannelNCOFrequenciesChipA = zeros(1,tx.num_fine_attr_channels); %MxFE0 Fine DUC NCO Frequencies [Hz]
        tx.ChannelNCOFrequenciesChipB = zeros(1,tx.num_fine_attr_channels); %MxFE1 Fine DUC NCO Frequencies [Hz]
        tx.ChannelNCOFrequenciesChipC = zeros(1,tx.num_fine_attr_channels); %MxFE2 Fine DUC NCO Frequencies [Hz]
        tx.ChannelNCOFrequenciesChipD = zeros(1,tx.num_fine_attr_channels); %MxFE3 Fine DUC NCO Frequencies [Hz]
        tx.MainNCOPhasesChipA = zeros(1,tx.num_coarse_attr_channels); %MxFE0 Coarse DUC NCO Phase Offsets [Degrees*1e3]
        tx.MainNCOPhasesChipB = zeros(1,tx.num_coarse_attr_channels); %MxFE1 Coarse DUC NCO Phase Offsets [Degrees*1e3]
        tx.MainNCOPhasesChipC = zeros(1,tx.num_coarse_attr_channels); %MxFE2 Coarse DUC NCO Phase Offsets [Degrees*1e3]
        tx.MainNCOPhasesChipD = zeros(1,tx.num_coarse_attr_channels); %MxFE3 Coarse DUC NCO Phase Offsets [Degrees*1e3]
        tx.ChannelNCOPhasesChipA = zeros(1,tx.num_fine_attr_channels); %MxFE0 Fine DUC NCO Phase Offsets [Degrees*1e3]
        tx.ChannelNCOPhasesChipB = zeros(1,tx.num_fine_attr_channels); %MxFE1 Fine DUC NCO Phase Offsets [Degrees*1e3]
        tx.ChannelNCOPhasesChipC = zeros(1,tx.num_fine_attr_channels); %MxFE2 Fine DUC NCO Phase Offsets [Degrees*1e3]
        tx.ChannelNCOPhasesChipD = zeros(1,tx.num_fine_attr_channels); %MxFE3 Fine DUC NCO Phase Offsets [Degrees*1e3]
        tx.NCOEnablesChipA = zeros(1,tx.num_fine_attr_channels); %MxFE0 Fine DUC Enables
        tx.NCOEnablesChipB = zeros(1,tx.num_fine_attr_channels); %MxFE1 Fine DUC Enables
        tx.NCOEnablesChipC = zeros(1,tx.num_fine_attr_channels); %MxFE2 Fine DUC Enables
        tx.NCOEnablesChipD = zeros(1,tx.num_fine_attr_channels); %MxFE3 Fine DUC Enables

I supposed that if the received signal power is lower, the value of minCodeValue=500 (Default) needs to be lowered, so i put at 300, but i not was able to find a math relation between this two elements. Is there a math logic behind that?

The algorithm works until the PLL alignment. With the Align_ADF4371s parameter equal to 0, the script works and the result (not so good) are the following:

But if i use  Align_ADF4371s=1 . I get the following error:

Error using matlabshared.libiio.base/cstatusid
Failed to re-create buffer.

Error in matlabshared.libiio.base/flushBuffers

Error in matlabshared.libiio.base/preGetData

Error in matlabshared.libiio.base/getData

Error in adi.common.Rx/stepImpl (line 77)
                [dataRAW, valid] = getData(obj);

Error in adi.QuadMxFE.Rx/stepImpl (line 445)
            [data,valid] = stepImpl@adi.common.Rx(obj);

Error in QuadMxFE_MCS_tx9_rx10_test2 (line 564)
        data = rx();

Can anyone help me to adapt the script at my new configuration? 

Thank you all!!

Best Regards!

-Lucian