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Generating hardware and software for customised Quad MxFE JESD204C parameters

I'm currently going through the process of getting the Quad MxFE up and running.

As part of this process, I'm needing an MxFE configuration that differs from the test cases that Analog offers, as I'd like to take samples from the ADCs directly without any decimation or filtering, with all 16 ADCs running at 1.5 GSPS.

As such, I'm needing to generate new FPGA hardware and a new Linux image with the following JESD204C parameters:

RX Mode 11.10, 1x1 decimation, L=4, M=4, S=2, Rx Rate = 24.75 GHz
TX Mode 11.10, 1x1 decimation, L=4, M=4, S=2, Rx Rate = 24.75 GHz

I've compiled the HDL made available from Analog for the Quad MxFE successfully using "make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_PLL_SEL=1 TX_PLL_SEL=1 REF_CLK_RATE=250 RX_JESD_L=4 RX_JESD_M=4 RX_JESD_S=2 TX_JESD_L=4 TX_JESD_M=4 TX_JESD_S=2 RX_KS_PER_CHANNEL=16 TX_KS_PER_CHANNEL=16". 

1st Question: Was that the correct approach or did I need to do something different to this?

I've now run into a stumbling block - I need to generate a Linux image to run on the VCU118 with a customised AD9081 driver that matches the above parameters, and I am struggling to do this.

The most up-to-date and closest documentation on how to do this is here:

I have tried using "make menuconfig" but two of the menu options, such as "JESD204 High-Speed Serial Interface Framework" and "JESD204 High-Speed Serial Interface Support", don't appear to be present.

2nd Question: Which options should I select with the latest version of the Linux kernel available from Analog to support the Quad MxFE?

I also see that I need to generate a device tree to define the configuration of the four AD9081s and the JESD204C interface. I can see an example file in the above link, "adi-ad9081-fmc-ebz.dtsi", but I am unsure where this needs to go.

3rd Question: Where does the device tree file defining the configuration of the four AD9081s and the JESD204C interface need to go?

4th Question: Once the Linux kernel has been generated, is this already in the correct form for running on the Xilinx VCU118 or do I need to perform some further steps to get the image into .strip file format?

EDIT: 5th Question that I've thought of: Do I only need to edit the Kernel configuration to make the alterations necessary to use the onchip PLL on the VCU118 or do I only need to alter the device tree?

Added additional question.
[edited by: Salisen at 2:57 PM (GMT -5) on 14 Jan 2022]