Quad MxFE test cases JESD parameters

Hi,

I was reading thorough the Quad MxFE user guide and was a little confused by the example JESD204C link parameters.

https://wiki.analog.com/resources/eval/user-guides/quadmxfe/quick-start

For example, in the final test case in the link above, we have 4 Tx / 4 Rx per MxFE. Looking at the Rx side, we have ADC JESD204C: Mode 29, L=4, M=8, N=N'=12. Giving the maximum line rate of 24.75 Gbps.

My question is: why in this case is M=8? We have 4 converters on the Rx per chip so surely M=4, giving a line rate of 12.375 Gbps.

What am I missing here? The same question also applies to the 2 Txs / 2 Rx test case, as well as the Tx side.

Thanks!

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  • +1
    •  Analog Employees 
    on Apr 28, 2021 4:34 PM

    Hi callum123,

    M is not the number of physical converters on the MxFE but rather "virtual" converters, so it is not necessarily equal to the number of physical DACs or ADCs on the chip.

    Take for example M=8, we have a real[-valued signal] coming into our ADCs then a real to complex conversion in the DDCs resulting in 4 'I' codes and 4 'Q' codes.

    To get to 24.75Gbps we use JESD_204C_Lane_Rate = (ADC_sample_rate/(total_decimation)*M*N'*66/64/L, where L is a maximum of 4 in our case.

    M=8 in Mode 24 because we're going through the 4 (physical) DACs and then going through DUCs creating 4x 'I' codes and 4x 'Q' codes. In Mode 23 M=4 because we're using 2 DACs (physical) and then going through 2 DUCs creating 2x 'I' codes and 2x 'Q' codes. If we were to bypass interpolation stages and use all 4 DACs of the MxFE our result is 4 'I' codes.

    To put it more simply, if we go through any interpolation (DUCs) or decimation (DDCs) stages we double M for the number of DACs or ADCs enabled, this is because of the real-to-complex conversion that needs to occur.

    Best,
    Michael

Reply
  • +1
    •  Analog Employees 
    on Apr 28, 2021 4:34 PM

    Hi callum123,

    M is not the number of physical converters on the MxFE but rather "virtual" converters, so it is not necessarily equal to the number of physical DACs or ADCs on the chip.

    Take for example M=8, we have a real[-valued signal] coming into our ADCs then a real to complex conversion in the DDCs resulting in 4 'I' codes and 4 'Q' codes.

    To get to 24.75Gbps we use JESD_204C_Lane_Rate = (ADC_sample_rate/(total_decimation)*M*N'*66/64/L, where L is a maximum of 4 in our case.

    M=8 in Mode 24 because we're going through the 4 (physical) DACs and then going through DUCs creating 4x 'I' codes and 4x 'Q' codes. In Mode 23 M=4 because we're using 2 DACs (physical) and then going through 2 DUCs creating 2x 'I' codes and 2x 'Q' codes. If we were to bypass interpolation stages and use all 4 DACs of the MxFE our result is 4 'I' codes.

    To put it more simply, if we go through any interpolation (DUCs) or decimation (DDCs) stages we double M for the number of DACs or ADCs enabled, this is because of the real-to-complex conversion that needs to occur.

    Best,
    Michael

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