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Issue with GPIO7 pulled low after a few seconds

Thread Summary

The user experienced GPIO7 being pulled low on the AD2437 chip, suspecting a configuration issue. However, the issue was resolved when it was discovered that the 3.3V rail was dropping below the supervisor circuit's threshold, causing a system reset. The AD2437 is assumed to be functioning correctly.
AI Generated Content
Category: Hardware
Product Number: AD2437

I am bringing up a new prototype, and have not even configured the AD2437 chip, but I see that a net connected to GPIO7 is being pulled low after a few seconds. I'm wondering why that might happen even though the default settings seemingly should leave GPIO7 tri-state (or so I think). When the chip is reset via its /RST pin, GPIO7 immediately floats and releases the net, but several seconds after it is pulled low again. The time it takes for GPIO7 to be pulled low starts out as long as a minute after powerup, but the cycles from /RST to GPIO7 pulled low get shorter over time.

First of all, I am not entirely certain that GPIO7 is being pulled low by the AD2437, but the rest of the chips on that net treat the connected pins as inputs, so the AD2437 is the most likely culprit. I am reworking the board to cut the trace to GPIO7 to isolate the problem.

Looking at the documentation, GPIO7 - besides being a general purpose input output pin - can be programmed to take on the roles of PDMCLK, RRSTRB, SPIBUSY, or GPIO Over Distance.

PDMCLK - this does not fit the symptoms, because a clock output would not be pulled low, but would oscillate.

RRSTRB - seems unlikely, since nothing has programmed reduced rate mode

SPIBUSY - again, nothing has programmed SPIPINCFG.SPIGPIOSEL away from the default

GPIO Over Distance - because this is an early prototype, I have not even connect the chip to a bus (A2B), so all remote operations should be impossible

I'm wondering if there is any sort of timeout or interrupt that might be assigned to GPIO7 that would explain this.

Also, if there are any AD2437 registers that I could change from their defaults to prevent this, I should be able to use the attached SigmaDSP to program those registers in the time between /RST and the issue.

Edit Notes

typo corrected
[edited by: SoundConsulting at 5:53 PM (GMT -4) on 26 Jul 2026]

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