Loudspeaker <-> EzKit <-> ADSP-21569-SOM <-> brkout <->AD2428WD1BZ <-> AD2428WC1BZ (mic)

I think the probing setup looks incorrect to me.. may be Ground connection issue? 

If I understand it correctly, 20msec per division points to 50Hz line signal. So, these are not actual signals from A2B. 

For A2B SYNC of 48KHz, the scope setting should be 20us/division.  

Thanks. This is my SRU init in CCES code. Can you give any idea?

void SRU_Init(void)
{
/* Enable DAI pins */
*pREG_PADS0_DAI0_IE = 0x1ffffe;
*pREG_PADS0_DAI1_IE = 0x1ffffe;

/*==========================================================================
* A2B Interface (DAI0) - DSP is Master
* DAI0_PIN02: BCLK output to AD2428
* DAI0_PIN03: SYNC output to AD2428
* DAI0_PIN04: DTX0 input from AD2428
*========================================================================*/

/* PCG0 BCLK -> DAI0_PIN02 (output to A2B) */
SRU(PCG0_CLKA_O, DAI0_PB02_I);
SRU(HIGH, DAI0_PBEN02_I); /* Enable output */

/* PCG0 SYNC -> DAI0_PIN03 (output to A2B) */
SRU(PCG0_FSA_O, DAI0_PB03_I);
SRU(HIGH, DAI0_PBEN03_I); /* Enable output */

/* DAI0_PIN04 -> SPORT0A Data Input (A2B DTX0) */
SRU(DAI0_PB04_O, SPT0_AD0_I);
SRU(LOW, DAI0_PBEN04_I); /* Input */

/* PCG0 BCLK -> SPORT0A Clock */
SRU(PCG0_CLKA_O, SPT0_ACLK_I);

/* PCG0 SYNC -> SPORT0A Frame Sync */
SRU(PCG0_FSA_O, SPT0_AFS_I);

/*==========================================================================
* DAC Interface (DAI1) - DAC is Master (existing setup)
* DAI1_PIN05: BCLK from DAC
* DAI1_PIN04: FS from DAC
* DAI1_PIN01: Data to DAC
*========================================================================*/

/* DAC BCLK input */
SRU2(LOW, DAI1_PBEN05_I);

/* DAC BCLK -> SPORT4A and SPORT4B Clock */
SRU2(DAI1_PB05_O, SPT4_ACLK_I);
SRU2(DAI1_PB05_O, SPT4_BCLK_I);

/* DAC FS input */
SRU2(LOW, DAI1_PBEN04_I);

/* DAC FS -> SPORT4A and SPORT4B Frame Sync */
SRU2(DAI1_PB04_O, SPT4_AFS_I);
SRU2(DAI1_PB04_O, SPT4_BFS_I);

/* SPORT4A Data -> DAC */
SRU2(SPT4_AD0_O, DAI1_PB01_I);
SRU2(HIGH, DAI1_PBEN01_I); /* Enable output */

/* ADC Data -> SPORT4B (for RX) */
SRU2(DAI1_PB06_O, SPT4_BD0_I);
SRU2(LOW, DAI1_PBEN06_I); /* Input */

/* DAC BCLK -> ADC (for DAC clock reference) */
SRU2(DAI1_PB05_O, DAI1_PB12_I);
SRU2(HIGH, DAI1_PBEN12_I);

/* DAC FS -> ADC FS */
SRU2(DAI1_PB04_O, DAI1_PB20_I);
SRU2(HIGH, DAI1_PBEN20_I);
}

I could not find any issue with SRU settings. It seems, you are able to discover the subnode with SYNC from DSP to A2B main. So I believe those signals from DSP should be correct.

So, now remaining question is, you are not able to probe it correctly, is it? Could you please check ground connections between boards or to probes? Please keep scope settings as 20us/div to see 48KHz SYNC signal. 

Thanks.

Hmmm. only SYNC makes 48kHz signal. and others make 60Hz signal...

I want to make  BCLK  122.288MHz...

Sorry, maybe I could not fully understand the "and others make 60Hz signal". Do you mean, other signals like BCLK, DTX0? 

BCLK cannot be 122.288MHz. Max BCLK spec is ~50MHz. I believe, you meant BCLK of 12.288MHz. In that case, the data bits would change at half rate (depending on bit pattern) ie. at 6.144MHz. So not sure which 60Hz signal you are referring to? Could you please clarify? 

What...?

I used AD2428 for TDM8, 48kHz and 32bits.

So I thought BCLK is 12,288,000 (8 * 48 * 32).

How should I set it up in this case?

void PCG_Init(void)
{
volatile uint32_t *pCTLA0 = pREG_PCG0_CTLA0;
volatile uint32_t *pCTLA1 = pREG_PCG0_CTLA1;
uint32_t ctla0_val, ctla1_val;
int delay = 0xFFFF;

/* 1. PCG */
*pCTLA0 = 0;
*pCTLA1 = 0;
while(delay--) { asm("nop;"); }

/*
* (BCLK)
* Bit 31 (CLKSRC) = 1 (Internal SCLK0)
* Bit 30 (FSSRC) = 0
* Bits 19:0 (CLKDIV) = 16 (400MHz)
*
* 400MHz / 16 = 25 MHz
*/
ctla1_val = (1u << 31) |
(0u << 30) |
(8 & 0xFFFFF);
*pCTLA1 = ctla1_val;

/*
* (Frame Sync)
* Bit 31 (CLKEN) = 1
* Bit 30 (FSEN) = 1
* Bits 19:0 (FSDIV) = 256
*
* 25MHz / 512 = 48.8 kHz
*/
ctla0_val = (1u << 31) |
(1u << 30) |
(512 & 0xFFFFF);
*pCTLA0 = ctla0_val;

DEBUG_INFORMATION("PCG Configured: SCLK0(200M) -> BCLK( 0x%08X ) -> SYNC( 0x%08X )\n", ctla1_val, ctla0_val);
}

I changed my PCG_init.

So i get BCLK 12MHz in oscilloscope is it strange?

ADI_PCG_CLK_INFO gClkInfo;
gClkInfo.eClkInput = ADI_PCG_CLK_CLKIN0; /* Clock Source */
gClkInfo.nDiv = 2u; /* Clock Divisor */
gClkInfo.bExternalTrigger = false; /* External Trigger */

ADI_PCG_FS_INFO gFsInfo;
gFsInfo.eClkInput = ADI_PCG_FS_CLKIN0; /* Clock Source */
gFsInfo.nDiv = 520u; /* Frame Sync Divisor */
gFsInfo.nPulseWidth = (gFsInfo.nDiv)/2u; /* Pulse Width */
gFsInfo.nPhase = 0; /* Phase */
gFsInfo.bExternalTrigger = false; /* External Trigger */
gFsInfo.eFsBypassMode = ADI_PCG_FSBYPASS_MODE_NORMAL; /* Bypass Mode */

adi_pcg_Init(ADI_PCG_DEV_A,&gClkInfo,&gFsInfo);

With TDM8x32-bit mode @48KHz, the BCLK would be 12.288MHz. So, your 12MHz signal looks correct. I believe 122.88MHz was a typo in your reply 

So, with this clock rate, the DTX would change at <6.144MHz rate, depending on data bit pattern. Are you seeing these signals at this rate on scope?