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ECC in AD2428

Category: Software
Product Number: AD2428


I would like to enable the ECC for upstream and downstream 24-bit/32-bit data slots. To suffice the requirement, I have set the Bit 7 and Bit 3 of A2B_SLOTFMT register.

I am using AD2428 as master in the custom host setup and EVAL-AD2428WB1BZ as a subnode.

My questions are,

  • how can I validate that the ECC is really working?
  • Is there is a way to inject ECC errors?
  • Is there is a way to identify that ECC error occurred and A2B has tried to recover it? 
  • Hi,

    ECC offers single error correction and multiple error detection.

    The ECC failure is captured as DPERR. With ECC for data slots, single bit error is corrected; no error is reported. If decode errors are seen on two or more bits of the data word, it is treated as bad. If the ECC logic reports an uncorrectable error, it is reported as DPERR.

    After enabling the ECC for data slots , A2B_GENERR register can be programmed to generate data parity errors. Writing to this register generates single bit error . Enabling ECC wouldn't report a data parity error as ECC logic would have corrected it. Disabling ECC would report it as Data parity error.